A comparison of computing-in-memory with non-volatile memory types and SRAM in DNN training
Source abstract
Abstract
In recent years, as Deep Neural Network (DNN) has been widely used in various artificial intelligence (AI) applications, the demands for energy efficiency and computational speed have continuously increased. Computing-in-Memory (CIM), as a potential solution, can significantly reduce the energy consumption and the delay caused by data transmission. In the paper, the CIM application based on spintronic device in DNN training is explored. Architecture for CIM using spintronic devices can efficiently perform the computational tasks of neural networks at the memory level. Comparison is conducted with the computation training based on SRAM, RRAM, and FeFET for a standard DNN training task with the same inference accuracy.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: Advanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · IoT and Edge/Fog Computing
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (20)
Show source-provided references
1. Efficient processing of deep neural networks: A tutorial and survey10.1109/jproc.2017.2761740 ↗
2. An overview of nonvolatile emerging memories—Spintronics for working memories10.1109/jetcas.2016.2547704 ↗
3. A compact model with spin-polarization asymmetry for nanoscaled perpendicular MTJs10.1109/ted.2017.2734967 ↗
4. Modeling of a magnetic tunnel junction for a multilevel STT-MRAM cell10.1109/tnano.2018.2875491 ↗
5. Research on thermal analysis method of 3D-stacked MRAM10.12263/DZXB.20220275 ↗
6. Spintronic logic-in-memory paradigms and implementations
7. NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning10.1109/tcad.2018.2789723 ↗
8. Compute-in-memory chips for deep learning: Recent trends and prospects10.1109/mcas.2021.3092533 ↗
9. CIMAT: Compute-in-memory architecture for on-chip training based on transpose SRAM Arrays10.1109/TC.2020.2980533 ↗
10. Vesti: Energy-Efficient in-memory computing accelerator for deep neural networks10.1109/tvlsi.2019.2940649 ↗
11. MRAM-based in-memory computing: Prospects and challenges
12. Temperature-resilient RRAM-based in-memory computing for DNN inference10.1109/mm.2021.3131114 ↗
13. Ferroelectric field-effect transistor-based 3-D NAND architecture for energy-efficient on-chip training accelerator10.1109/jxcdc.2021.3057856 ↗
14. Spin-based architecture for compressed DNN
15. Monolithically integrated RRAM- and CMOS-based in-memory computing optimizations for efficient deep learning10.1109/mm.2019.2943047 ↗
16. PUFFIN: Efficient DNN training with FeFET
17. Energy efficient ternary computation unit using differential spin Hall effect MRAM10.1088/1361-6641/acad95 ↗
18. Accurate deep neural network inference using computational phase-change memory
19. A 3-8 bit reconfigurable hybrid ADC architecture with successive-approximation and single-slope stages for computing in memory10.1109/ISCAS48785.2022.9937285 ↗
20. High-efficiency data conversion interface for reconfigurable function-in-memory computing10.1109/TVLSI.2022.3179621 ↗