Si-ring quantum-well GAA nanowire FET for 5 nm node CMOS integration

A novel structure for gate all-around (GAA) NW FET in the 5 nm scale has been proposed in this paper. This device consists of a germanium nanowire structure, the channel of which is surrounded by a ring-shaped silicon layer. In addition, a high-K dielectric has been used as the gate insulator. The performance of the device and its electrical characteristics have been determined using three-dimensional numerical simulation. The simulation results indicated that the proposed structure exhibits better performance compared to conventional GAA FET and Ge-ring QW GAA FET. Moreover, the on-current in nFET and pFET states was determined to be almost symmetrical, an essential factor in the design of integrated circuits. Subsequently, the efficiency of the proposed device was evaluated in the CMOS inverter and the static random access memory cell and was shown to be a remarkable improvement over the reported devices.