journal article·2026-06-04Open access

Reconfigurable Selector‐Only Memory (SOM) for Scalable Neuromorphic Computing

Jin‐Yu Wen, Chuan‐Qi Yi, Ya‐Ru Zhang, Bin‐Hao Wang, Zi‐Xuan Liu, Chun‐Yu Zhou, Hao Tong, Xiang‐Shui Miao

Abstract

ABSTRACT Highly scalable reconfigurable neuromorphic devices are critical for addressing continual‐learning challenges in artificial intelligence. However, the scalability of existing reconfigurable devices is severely constrained by limited operating margins and insufficient process maturity. Here, we propose selector‐only memory (SOM) as a scalable device candidate. Its volatile threshold switching and programmable nonvolatile threshold window are operationally decoupled, and it is compatible with in‐line fabrication and 3D stacking. We demonstrate an In‐doped GeSe SOM that enables neuron–synapse reconfigurability within a single cell. By leveraging intrinsic parasitic capacitance, we implement a capacitor‐free leaky integrate‐and‐fire neuron and validate all‐or‐none firing, integrate‐and‐fire dynamics, and input‐controlled firing‐rate modulation using experiments and an equivalent model. For synapses, we propose a one‐shot subthreshold‐conductance readout method. With a unified reverse‐subthreshold pulse scheme, 16 programmed conductance states are obtained through one‐shot subthreshold readout, and most states remain distinguishable over 10 4 s. Finally, SOM‐parameter‐based simulations on a Growing‐When‐Required MNIST task achieve 2.67× higher accuracy with 70% of the nodes and shrink to 58% after rollback. These results indicate that SOM provides a promising selector‐derived device concept for scalable reconfigurable neuromorphic hardware.
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Research context

OpenAlex topics: Advanced Memory and Neural Computing · Neural Networks and Reservoir Computing · Ferroelectric and Negative Capacitance Devices

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

School of Integrated Circuits Huazhong University of Science and Technology Wuhan China

Institute of Artificial Intelligence Huazhong University of Science and Technology Wuhan China

Hubei Yangtze Memory Laboratories Wuhan China

Funding

National Key Research and Development Program of China · National Natural Science Foundation of China

References (46)

Show source-provided references
1. 10.1126/science.abj794310.1126/science.abj7943 ↗
2. 10.1016/j.neunet.2019.01.01210.1016/j.neunet.2019.01.012 ↗
3. 10.1073/pnas.161183511410.1073/pnas.1611835114 ↗
4. 10.1038/s42256‐018‐0006‐z10.1038/s42256‐018‐0006‐z ↗
5. 10.1002/adma.20230106310.1002/adma.202301063 ↗
6. 10.1063/5.013183810.1063/5.0131838 ↗
7. 10.1038/s41467‐025‐62306‐810.1038/s41467‐025‐62306‐8 ↗
8. Y.Fu Y.Zhou andX.Huang “Forming‐free and Annealing‐free V/VOx/HfWOx/Pt Device Exhibiting Reconfigurable Threshold and Resistive Switching With High Speed (<30 ns) and High Endurance (>1012/>1010) ” in2021 IEEE International Electron Devices Meeting (IEDM) San Francisco CA USA (IEEE 2021) 1–4.10.1109/IEDM19574.2021.9720551 ↗
9. 10.1002/adfm.20211199610.1002/adfm.202111996 ↗
10. 10.1088/0957‐4484/27/35/35520510.1088/0957‐4484/27/35/355205 ↗
11. 10.1073/pnas.210393411810.1073/pnas.2103934118 ↗
12. 10.1021/acs.nanolett.4c0247010.1021/acs.nanolett.4c02470 ↗
13. 10.1021/acs.nanolett.4c0131910.1021/acs.nanolett.4c01319 ↗
14. 10.1021/acs.jpclett.5c0018410.1021/acs.jpclett.5c00184 ↗
15. 10.1038/s41598‐025‐15251‐x10.1038/s41598‐025‐15251‐x ↗
16. 10.1038/s41467‐022‐29727‐110.1038/s41467‐022‐29727‐1 ↗
17. 10.1038/s41467‐025‐59603‐710.1038/s41467‐025‐59603‐7 ↗
18. 10.1038/s41467‐022‐30432‐210.1038/s41467‐022‐30432‐2 ↗
19. 10.1038/s41467‐024‐48631‐410.1038/s41467‐024‐48631‐4 ↗
20. 10.1038/s41586‐024‐08253‐810.1038/s41586‐024‐08253‐8 ↗
21. T.Ravsher R.Degraeve andD.Garbin “Polarity‐dependent Threshold Voltage Shift in Ovonic Threshold Switches: Challenges and Opportunities ” in2021 IEEE International Electron Devices Meeting (IEDM) (IEEE 2021) 1–4 https://doi.org/10.1109/IEDM19574.2021.9720649.10.1109/IEDM19574.2021.9720649 ↗
22. S.Hong H.Choi andJ.Park “Extremely High Performance High Density 20Nm Self‐selecting Cross‐point Memory for Compute Express Link ” in2022 International Electron Devices Meeting (IEDM) (IEEE 2022) 1–4 https://doi.org/10.1109/IEDM45625.2022.10019415.10.1109/IEDM45625.2022.10019415 ↗
23. 10.1109/TED.2023.325249110.1109/TED.2023.3252491 ↗
24. 10.1007/s11432‐023‐3907‐x10.1007/s11432‐023‐3907‐x ↗
25. 10.1063/5.012717710.1063/5.0127177 ↗
26. J.Lee Y.Seo andS.Ban “Enhancing Se‐based Selector‐only Memory with Ultra‐fast Write Speed (∼10 ns) and Superior Retention Characteristics (>10 years at RT) via Material Design and UV Treatment Engineering ” inProceedings of the IEEE 2023 International Electron Devices Meeting (IEDM) San Francisco CA USA(2023) 1–4.10.1109/IEDM45741.2023.10413815 ↗
27. J.Yi M.Kim andJ.Seo “The Chalcogenide‐based Memory Technology Continues: Beyond 20Nm 4‐deck 256Gb Cross‐point Memory ” in2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Kyoto Japan (IEEE 2023) 1–2.10.23919/VLSITechnologyandCir57934.2023.10185210 ↗
28. M.Kim Y.Bae andJ.Park “First Demonstration of Fully Integrated 16 Nm Half‐Pitch Selector Only Memory (SOM) for Emerging CXL Memory ” in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Honolulu HI USA (IEEE 2024) 1–2.10.1109/VLSITechnologyandCir46783.2024.10631351 ↗
29. I. M.Park K. W.Lee andJ. H.Park “Enhanced Endurance Characteristics in High Performance 16Nm Selector Only Memory (SOM) ” in2023 International Electron Devices Meeting (IEDM) San Francisco CA USA (IEEE 2023) 1–4.10.1109/IEDM45741.2023.10413748 ↗
30. F.Pellizzer A.Pirovano R.Bez andR. L.Meyer “Status and Perspectives of Chalcogenide‐based CrossPoint Memories ” in2023 International Electron Devices Meeting (IEDM) San Francisco CA USA (IEEE 2023) 1–4 https://doi.org/10.1109/IEDM45741.2023.10413669.10.1109/IEDM45741.2023.10413669 ↗
31. J. H.Park C. H.Lee andW. H.Park “Scalable Fabrication and Demonstration of the First Fully Integrated 14Nm 2‐Stack SOM (Selector Only Memory) Device ” in2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Kyoto Japan (IEEE 2025) 1–3.10.23919/VLSITechnologyandCir65189.2025.11075063 ↗
32. S.Ban J.Lee T.Kim andH.Hwang “Simple Binary in‐Te OTS With Sub‐nm HfOxBuffer Layer for 3D Vertical X‐point Memory Applications ” in2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Kyoto Japan (IEEE 2023) 1–2 https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185213.10.23919/VLSITechnologyandCir57934.2023.10185213 ↗
33. 10.1109/LED.2024.349577810.1109/LED.2024.3495778 ↗
34. S.Clima F.Ducry andD.Garbin “Selector Only Memory: Exploring Atomic Mechanisms From First‐Principles ” in2024 IEEE International Electron Devices Meeting (IEDM) San Francisco CA USA (IEEE 2024) 1–4 https://doi.org/10.1109/IEDM50854.2024.10873555.10.1109/IEDM50854.2024.10873555 ↗
35. F.Hatem Z.Chai andW.Zhang “‐xOTS Selectors by Using a Novel Refreshing Program Scheme ” in2019 IEEE International Electron Devices Meeting (IEDM) San Francisco CA USA (IEEE 2019) 1–4.
36. 10.1039/D3TC00448A10.1039/D3TC00448A ↗
37. M.Yamaguchi R.Degraeve andD.Garbin “Understanding the Cycling‐Dependent Threshold Voltage Instability in OTS Devices ” in2022 International Electron Devices Meeting (IEDM)(IEEE 2022) 5.1.1–5.1.4 https://doi.org/10.1109/IEDM45625.2022.10019444.10.1109/IEDM45625.2022.10019444 ↗
38. S.Kabuyanagi D.Garbin andA.Fantini “Understanding of Tunable Selector Performance in Si‐Ge‐As‐Se OTS Devices by Extended Percolation Cluster Model Considering Operation Scheme and Material Design ” in2020 IEEE Symposium on VLSI Technology Honolulu HI USA (IEEE 2020) 1–2 https://doi.org/10.1109/VLSITechnology18217.2020.9265011.10.1109/VLSITechnology18217.2020.9265011 ↗
39. 10.1063/1.277368810.1063/1.2773688 ↗
40. 10.1103/PhysRevB.78.05220110.1103/PhysRevB.78.052201 ↗
41. he Mechanism Behind Ovonic Threshold Switching Revealed10.1126/sciadv.aay2830 ↗
42. L.Jung J.Lee Y.Seo andH.Hwang “Achieving 3‐bit Operation in Selector‐only‐memory by Controlling Variability With Microwave Annealing and Bipolar Pulse Scheme ” in2024 IEEE International Electron Devices Meeting (IEDM) San Francisco CA USA (IEEE 2024) 1–4.10.1109/IEDM50854.2024.10873515 ↗
43. 10.1016/j.mee.2019.11099010.1016/j.mee.2019.110990 ↗
44. 10.1016/j.chaos.2024.11585610.1016/j.chaos.2024.115856 ↗
45. 10.1016/j.chaos.2025.11676010.1016/j.chaos.2025.116760 ↗
46. 10.1002/adma.20251744010.1002/adma.202517440 ↗