Hybrid Contact for High‐Performance MoS ₂ Transistors via Hard‐Mask Scanning Probe Lithography

Abstract The scaling down of transistors in silicon‐based complementary metal‐oxide‐semiconductor (CMOS) technology has reached critical limits, necessitating the exploration of novel materials and architectures. 2D semiconductors have emerged as promising candidates for continuing Moore's law beyond traditional silicon due to their atomic‐scale thickness and superior electrostatic control, which mitigate short channel effects. However, realizing the full potential of 2D materials in industrial applications requires overcoming challenges in fabricating scalable and CMOS‐compatible devices, particularly concerning metal‐semiconductor contacts. Here, a hybrid‐contact configuration is presented by developing a hard‐mask scanning probe lithography (SPL) for high‐performance molybdenum disulfide (MoS ₂ ) field‐effect transistors (FETs). After systematically comparing with the fabricated top‐contact and edge‐contact configurations, the hybrid‐contact substantially improves carrier injection efficiency, enabling an enhanced on‐current of 50.5 µA·µm⁻¹, an on/off ratio exceeding 5 × 10 ¹⁰ , a reduced contact resistance of 2.14 kΩ·µm, and a Schottky barrier height of 26 meV, which is evidently illustrated by using the equivalent resistor network. The hard‐mask SPL also facilitates the high‐resolution nanoscale patterning on MoS ₂ flakes with a feature size of ≈18 nm. This hybrid‐contact configurations along with hard‐mask SPL demonstrate potentials in fabricating high‐performance 2D FETs, paving the way for their practical application in future electronic devices.