A Vertically Stackable Split‐Gate Amorphous Oxide Semiconductor 2T0C DRAM for Reducing Capacitive Coupling and Sneak‐Path Current

ABSTRACT Two‐transistor zero‐capacitor (2T0C) dynamic random access memory (DRAM) based on an amorphous oxide semiconductor (AOS) offers a promising solution to the capacitor scaling limitations of conventional one‐transistor one‐capacitor (1T1C) DRAM, providing long retention time and non‐destructive read operation. However, it faces cell‐level limitations, such as storage‐node (SN) voltage degradation caused by capacitive coupling from parasitic capacitances. It also suffers from array‐level issues such as sneak‐path currents and IR drops in the read word‐lines (RWL), as because RWLs and read bit‐lines (RBL) are assigned to the source and drain of the read transistor. To address these limitations, a split‐gate AOS 2T0C DRAM is proposed, featuring a split‐gate read transistor that has two gates along the channel. A common ground node effectively reduces parasitic capacitances, enhancing SN voltage stability. Moreover, by utilizing a gate‐controlled RWL structure, sneak‐path currents and IR drops in the RWL are mitigated. The fabrication process is simplified by utilizing the AOS channel of the write transistor as the SN, reducing fabrication complexity in vertically stacked structures. As a result, a retention window of 10 ⁷ over 1200 s and 52 multi‐level operations are achieved, while minimizing capacitive coupling, sneak‐path currents, and IR drops in RWL.