Strategical Implementation of Vertical Stack Configuration with Planar‐ and Vertical‐Channel Thin Film Transistors Using a Single InGaZnO Active Layer for 3D Device Integration

Abstract To eliminate the thermal impact on oxide semiconductor channels during the device integration, a novel stacking strategy is explored for 3D integration of oxide thin‐film transistors (TFTs). In this configuration, lower‐layer planar‐channel TFT (PTFT) and upper‐layer vertical‐channel TFTs (VTFTs) are designed in a vertical‐stacking arrangement with an inter‐electrode dielectric (IED) and a single active layer. This novel configuration is termed single‐active‐stacked TFT (SAS‐TFT). The choice of IED is identified as an important factor for the operational functionality of the bottom PTFT. The PTFT using an Al ₂ O ₃ IED demonstrates superior device performance in comparison to that using an SiO ₂ IED. The disparities in process conditions between two IEDs are responsible for more severe process damage to the back‐channel interface and source/drain electrodes of the PTFT using an SiO ₂ IED, attributable to the creation of additional defect states in the channel and the increase in contact resistance. Alternatively, the top VTFTs arranged in the SAS‐TFT employing an Al ₂ O ₃ IED exhibit sound device operations without any marked device‐stacking process damage. The top VTFT demonstrates a high current drivability of 26.8 µA µm ^‒1 and an on/off current ratio of 10 ¹⁰ . The SAS‐TFT is a successful innovation achieved through the exploration of optimal process conditions.