journal article·2017-06

Nanowire Transistors: Manipulating III–V Nanowire Transistor Performance via Surface Decoration of Metal‐Oxide Nanoparticles (Adv. Mater. Interfaces 12/2017)

Fengyun Wang, SenPo Yip, Guofa Dong, Fei Xiu, Longfei Song, Zaixing Yang, Dapan Li, Tak Fu Hung, Ning Han, Johnny C. Ho

Advanced Materials Interfaces· Volume 4· Issue 12
Publisher page

Abstract

Ning Han, Johnny C. Ho, and co-workers develop a metal-oxide decoration scheme to modulate threshold voltage of III-V nanowire FETs through adjusting free carriers in the nanowire channel via decorating various metal-oxide nanoparticles with different work functions in article number 1700260. Low-power InAs nanowire NMOS inverters, based on pristine depletion-mode and metal-oxide nanoparticles decorated enhancement-mode InAs NW-parallel-arrayed transistors, can demonstrate the versatility of this technique for future high-performance nanoelectronics.
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Research context

OpenAlex topics: Nanowire Synthesis and Applications · Advancements in Semiconductor Devices and Circuit Design

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Affiliations

College of Physics and Cultivation Base for State Key Laboratory Qingdao University Qingdao 266071 P. R. China

Department of Physics and Materials Science City University of Hong Kong 83 Tat Chee Avenue Kowloon Hong Kong

State Key Laboratory of Millimeter Waves City University of Hong Kong 83 Tat Chee Avenue Kowloon Hong Kong

Shenzhen Research Institute City University of Hong Kong Shenzhen 518057 P. R. China

Key Laboratory of Flexible Electronics (KLOFE) and Institute of Advanced Materials (IAM) Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM) Nanjing Tech University (NanjingTech) Nanjing 211816 P. R. China

School of Microelectronics and Center of Nanoelectronics Shandong University Jinan 250100 P. R. China

State Key Laboratory of Multiphase Complex Systems Institute of Process Engineering Chinese Academy of Sciences Beijing 100190 P. R. China

References

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