Interfacial Thermal Transport and Energy Dissipation in Multilayer PdSe₂ Field Effect Transistors

Abstract The continuous miniaturization of 2D electronic circuits results in increased power density during device operation, leading to heat localization and placing higher demands on their performance thresholds. The risk to thermal breakdown and subsequent damage, due to the energy dissipation in the 2D semiconductor field‐effect transistors (FETs) supported on the bulk substrates, represents a significant challenge in maintaining their optimal performance. Herein, this study investigates energy dissipation behavior in multilayer PdSe₂ FETs for the first time. The high‐field breakdown behavior is firstly studied in multilayer PdSe₂ FETs on SiO₂/Si substrates, where a maximum current density of ≈2.74 MA cm⁻² is observed, which is comparable to that of multilayer black phosphorus FET and significantly higher—by about five times—than that of multilayer MoS₂ FET. Additionally, the thermal boundary conductance (TBC) of PdSe₂/SiO₂ interface is measured at room temperature using Raman thermometry. The TBC is found to be ≈12–13 MW m⁻² K⁻¹, which is relatively low compared to the other known solid–solid interfaces, indicating that enhancing the performance of PdSe₂ FETs can be possible by optimizing the TBC at the PdSe₂/SiO₂ interface. These findings provide valuable insights for design of high‐quality and high‐performance PdSe₂ electronic and optoelectronic devices.