journal article·2022-05

Impact of Strategic Approaches for Improving the Device Performance of Mesa-shaped Nanoscale Vertical-Channel Thin-Film Transistors Using Atomic-Layer Deposited In–Ga–Zn–O Channel Layers

Hyun-Min Ahn, Young-Ha Kwon, Nak-Jin Seong, Kyu-Jeong Choi, Chi-Sun Hwang, Sung-Min Yoon

Electronic Materials Letters· Volume 18· Issue 3
Publisher page

Abstract

Abstract The effect of two strategic approaches, such as modification of active layer geometry and control of active channel composition, were investigated to improve the on/off ratio (ION/IOFF) and field-effect mobility (µFE) of mesa-shaped nanoscale vertical-channel thin-film-transistor (VTFT). The SiO2 spacer was deposited by using plasma-enhanced chemical vapor deposition and patterned via plasma etching process with Ar/CF4 gas mixtures to form a vertical sidewall, corresponding to a channel length of 170 nm. The gate-stack structures including an In–Ga–Zn–O (IGZO) active layer were deposited by atomic layer deposition with a complete conformality along the spacer sidewall. The ION/IOFF of the IGZO VTFT was significantly enhanced from 6.7 × 103 to 2.1 × 109 by lowering the off-state current when the layout geometry of active layer was properly designed to eliminate the uncontrolled current path between the vertically separated source and drain (S/D) electrodes. Furthermore, the µFE was improved from 0.3 to 2.2 cm2/Vs by enhancing the ION when the In/Ga ratio increased to 1.4 by controlling the In contents within the IGZO active channel. The device also showed robust stabilities under positive/negative gate-bias stresses at 2 MV/cm for 104 s. However, still low a µFE was suggested to originate from two detrimental issues of back-channel effects on spacer sidewall and contact resistance between the channel and S/D electrodes. Alternatively, it was confirmed that the increase in indium contents within the IGZO channel could be a useful way to reduce the contact resistance between the channel and S/D electrodes. Graphical Abstract
Source: expertdata · Quality: candidate unverified · Source record ↗

Research context

OpenAlex topics: Thin-Film Transistor Technologies · Semiconductor materials and devices · ZnO doping and properties

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

References (48)

Show source-provided references
1. Hattab, G., Hatzipanayioti, A., Klimova, A., Pfeiffer, M., Klausing, P., Breucha, M., von Bechtolsheim, F., Helmert, J.R., Weitz, J., Pannasch, S.: Investigating the utility of VR for spatial understanding in surgical planning: evaluation of head-mounted to desktop display. Sci. Rep. 11, 1–11 (2021)10.1038/s41598-021-92536-x ↗
2. Valentine, A., van der Veen, T., Kenworthy, P., Hassan, G.M., Guzzomi, A.L., Khan, R.N., Male, S.A.: Using head mounted display virtual reality simulations in large engineering classes: operating vs observing. Australas. J. Educ. Technol. 37, 119–136 (2021)10.14742/ajet.5487 ↗
3. Menin, A., Torchelsen, R., Nedel, L.: An analysis of VR technology used in immersive simulations with a serious game perspective. IEEE Comput. Graph. Appl. 38, 57–73 (2018)10.1109/MCG.2018.021951633 ↗
4. Jang, H.J., Lee, J.Y., Kwak, J.H., Lee, D.H., Park, J.H., Lee, B.H., Noh, Y.Y.: Progress of display performances: AR, VR, QLED, OLED, and TFT. J. Inf. Disp. 20, 1–8 (2019)10.1080/15980316.2019.1572662 ↗
5. Lee, S.H., Lee, K.H., Nam, Y.Y., Ko, J.B., Yeom, H.I., Hwang, C.S., Park, S.H.K.: Effect of channel defining layer on the vertical oxide TFTs for the application to the ultra high resolution display. SID Int. Symp. Dig. Tech. Pap. 48, 389–392 (2017)10.1002/sdtp.11642 ↗
6. Hwang, C.S., Kim, Y.H., Choi, J.H., Pi, J.E., Kim, G.H., Yang, J.H., Hwang, C.Y., Kim, J.Y., Kim, H.O., Lee, W.J.: Achieving 1µm pixel pitch display for electronic holography. In: Proceedings of the SPIE, Advances in display technologies X, vol. 11304, pp. 113040L. (2020)10.1117/12.2549474 ↗
7. Choi, J.H., Yang, J.H., Pi, J.E., Hwang, C.Y., Kim, Y.H., Kim, G.H., Kim, H.O., Hwang, C.S.: The new route for realization of 1-µm-pixel-pitch high-resolution displays. J. Soc. Inf. Disp. 27, 487–496 (2019)10.1002/jsid.821 ↗
8. Choi, J.H., Yang, J.H., Pi, J.E., Hwang, C.Y., Choi, K.H., Kim, H.O., Kwon, O.S., Hwang, C.S.: 1-µm short-channel oxide thin-film transistors with triangular gate spacer. IEEE Electron. Device Lett. 38, 1398–1400 (2017)10.1109/LED.2017.2748102 ↗
9. Choi, J.H., Pi, J.E., Hwang, C.Y., Yang, J.H., Kim, G.H., Kim, Y.H., Kim, H.O., Kwon, O.S., Park, E.S., Hwang, C.S.: Toward sub-micron oxide thin‐film transistors for digital holography. J. Soc. Inf. Disp. 25, 126–135 (2017)10.1002/jsid.535 ↗
10. Moradi, M., Fomani, A.A., Nathan, A.: Effect of gate dielectric scaling in nanometer scale vertical thin film transistors. Appl. Phys. Lett. 99, 223503 (2011)10.1063/1.3664217 ↗
11. Nogueira, G.L., Ozório, M.S., Silva, M.M., Morais, R.M., Alves, N.: Middle electrode in a vertical transistor structure using an Sn layer by thermal evaporation. Electron. Mater. Lett. 14, 319 (2018)10.1007/s13391-018-0034-1 ↗
12. Risch, L., Krautschneider, W.H., Hofmann, F., Schafer, H., Aeugle, T., Rosner, W.: Vertical MOS transistors with 70 nm channel length. IEEE Trans. Electron Devices 43, 1495–1498 (1996)10.1109/16.535340 ↗
13. Zhao, T., Cao, M., Saraswat, K.C., Plummer, J.D.: A vertical submicron polysilicon thin-film transistor using a low temperature process. IEEE Electron Device Lett. 15, 415–417 (1994)10.1109/55.320986 ↗
14. Moradi, M., Nathan, A., Haverinen, H.M., Jabbour, G.E.: Vertical transistor with ultrathin silicon nitride gate dielectric. Adv. Mater. 21, 4505–4510 (2009)10.1002/adma.200900757 ↗
15. Stutzmann, N., Friend, R.H., Sirringhaus, H.: Self-aligned, vertical-channel, polymer field-effect transistors. Science 299, 1881–1884 (2003)10.1126/science.1081279 ↗
16. Yang, T., Xia, Z., Shi, D., Ouyang, Y., Huo, Z.: Analysis and optimization of threshold voltage variability by polysilicon grain size simulation in 3D NAND flash memory. IEEE J. Electron Devices Soc. 8, 140–144 (2020)10.1109/JEDS.2020.2970450 ↗
17. Jia, X., Jin, L., Hou, W., Wang, Z., Jiang, S., Li, K., Huang, D., Liu, H., Wei, W., Lu, J.: Impact of cycling induced intercell trapped charge on retention charge loss in 3-D NAND flash memory. IEEE J. Electron Devices Soc. 8, 62–66 (2020)10.1109/JEDS.2019.2963473 ↗
18. Zou, X., Jin, L., Yan, L., Zhang, Y., Ai, D., Zhao, C., Xu, F., Li, C., Huo, Z.: The influence of grain boundary interface traps on electrical characteristics of top select gate transistor in 3D NAND flash memory. Solid-State Electron. 153, 67–73 (2019)10.1016/j.sse.2018.12.007 ↗
19. Seo, J.H., Yoon, Y.J., Yu, E.S., Sun, W.J., Shin, H.S., Kang, I.M., Lee, J.H., Cho, S.J.: Fabrication and characterization of a thin-body poly-Si 1T DRAM with charge-trap effect. IEEE Electron Device Lett. 40, 566–569 (2019)10.1109/LED.2019.2901003 ↗
20. Jeon, S.H., Benayad, A., Ahn, S.E., Park, S.H., Song, I.H., Kim, C.J., Chung, U.I.: Short channel device performance of amorphous InGaZnO thin film transistor. Appl. Phys. Lett. 99, 082104 (2011)10.1063/1.3623426 ↗
21. Nomura, K., Ohta, H., Takagi, A., Kamiya, T., Hirano, M., Hosono, H.: Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 432, 488–492 (2004)10.1038/nature03090 ↗
22. Fortunato, E., Barquinha, P., Martins, R.: Oxide semiconductor thin-film transistors: a review of recent advances. Adv. Mater. 24, 2945–2986 (2012)10.1002/adma.201103228 ↗
23. Nomura, K., Takagi, A., Kamiya, T., Ohta, H., Hirano, M., Hosono, H.: Amorphous oxide semiconductors for high-performance flexible thin-film transistors. Jpn. J. Appl. Phys. 45, 4303 (2006)10.1143/JJAP.45.4303 ↗
24. Lee, S.Y.: Comprehensive review on amorphous oxide semiconductor thin film transistor. Trans. Electr. Electron. Mater. 21, 235–248 (2020)10.1007/s42341-020-00197-w ↗
25. Cho, S.Y., Shin, Y.S., Seok, Y.C., Kim, H.W., Yoon, J.Y., Choi, R., Lee, J.H.: Improving electrical stability of a-InGaZnO thin-film transistors with thermally deposited self-assembled monolayers. Electron. Mater. Lett. 16, 451 (2020)10.1007/s13391-020-00232-1 ↗
26. Park, J., Kim, H., Choi, P., Jeon, B., Lee, J., Oh, C., Kim, B., Choi, B.: Effect of ALD- and PEALD-grown Al2O3 gate insulators on electrical and stability properties for a-IGZO thin-film transistor. Electron. Mater. Lett. 17, 299 (2021)10.1007/s13391-021-00282-z ↗
27. Petti, L., Aguirre, P., Münzenrieder, N., Salvatore, G.A., Zysset, C., Frutiger, A., Büthe, L., Vogt, C., Tröster, G.: Mechanically flexible vertically integrated a-IGZO thin-film transistors with 500 nm channel length fabricated on free standing plastic foil. In: 2013 IEEE International Electron Devices Meet, pp. 11–14 (2013)10.1109/IEDM.2013.6724609 ↗
28. Rha, H.S., Jung, J.S., Jung, S.Y., Chung, Y.J., Kim, U.K., Hwang, E.S., Park, B.K., Park, T.J., Choi, J.H., Hwang, C.S.: Vertically integrated submicron amorphous-In2Ga2ZnO7 thin film transistor using a low temperature process. Appl. Phys. Lett. 100, 203510 (2012)10.1063/1.4717621 ↗
29. Kim, Y.M., Kang, H.B., Kim, G.H., Hwang, C.S., Yoon, S.M.: Improvement in device performance of vertical thin-film transistors using atomic layer deposited IGZO channel and polyimide spacer. IEEE Electron Device Lett. 38, 1387–1389 (2017)10.1109/LED.2017.2736000 ↗
30. Choi, S.N., Yoon, S.M.: Implementation of In–Ga–Zn–O thin-film transistors with vertical channel structures designed with atomic-layer deposition and silicon spacer steps. Electron. Mater. Lett. 17, 485–492 (2021)10.1007/s13391-021-00307-7 ↗
31. Leskelä, M., Ritala, M.: Atomic layer deposition chemistry: recent developments and future challenges. Angew. Chem. 42, 5548–5554 (2003)10.1002/anie.200301652 ↗
32. Miikkulainen, V., Leskelä, M., Ritala, M., Puurunen, R.L.: Crystallinity of inorganic films grown by atomic layer deposition: overview and general trends. J. Appl. Phys. 113, 2 (2013)10.1063/1.4757907 ↗
33. Kim, H.R., Kim, G.H., Seong, N.J., Choi, K.J., Kim, S.K., Yoon, S.M.: Comparative studies on vertical-channel charge-trap memory thin-film transistors using In–Ga–Zn–O active channels deposited by sputtering and atomic layer depositions. Nanotechnology 31, 435702 (2020)10.1088/1361-6528/aba46e ↗
34. Ko, S.B., Seong, N.J., Choi, K.J., Yoon, S.J., Choi, S.N., Yoon, S.M.: Cationic compositional effects on the bias-stress stabilities of thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition. J. Mater. Chem. C 7, 6059–6069 (2019)10.1039/C9TC01164A ↗
35. Ryoo, H.J., Ahn, H.M., Seong, N.J., Choi, K.J., Hwang, C.S., Chang, S.J., Yoon, S.M.: Device characterization of nanoscale vertical-channel transistors implemented with a mesa-shaped SiO2 spacer and an In–Ga–Zn–O active channel. ACS Appl. Electron. Mater. 3, 4189–4196 (2021)10.1021/acsaelm.1c00631 ↗
36. Ryoo, H.J., Seong, N.J., Choi, K.J., Yoon, S.M.: Implementation of oxide vertical channel TFTs with sub-150 nm channel length using atomic-layer deposited IGZO active and HfO2 gate insulator. Nanotechnology 32, 255201 (2021)10.1088/1361-6528/abcbc4 ↗
37. Cho, M.H., Kim, M.J., Seul, H., Yun, P.S., Bae, J.U., Park, K.S., Jeong, J.K.: Impact of cation compositions on the performance of thin-film transistors with amorphous indium gallium zinc oxide grown through atomic layer deposition. J. Inf. Disp. 20, 73–80 (2019)10.1080/15980316.2018.1540365 ↗
38. Cho, M.H., Seol, H.J., On, N.R., Kim, T.K., Yun, P.S., Bae, J.U., Park, K.S., Jeong, J.K.: High performance a-IGZO thin‐film transistors grown by atomic layer deposition: cation combinatorial approach. SID Int. Symp. Dig. Tech. Pap. 50, 1259–1262 (2019)10.1002/sdtp.13162 ↗
39. Illiberi, A., Cobb, B., Sharma, A., Grehl, T., Brongersma, H., Roozeboom, F., Gelinck, G., Poodt, P.: Spatial atmospheric atomic layer deposition of InxGayZnzO for thin film transistors. ACS Appl. Mater. Interfaces 7, 3671–3675 (2015)10.1021/am508071y ↗
40. Yoon, S.J., Seong, N.J., Choi, K.J., Shin, W.C., Yoon, S.M.: Investigations on the bias temperature stabilities of oxide thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition. RSC Adv. 8, 25014–25020 (2018)10.1039/C8RA03639J ↗
41. Yoon, S.M., Seong, N.J., Choi, K.J., Seo, G.H., Shin, W.C.: Effects of deposition temperature on the device characteristics of oxide thin-film transistors using In–Ga–Zn–O active channels prepared by atomic-layer deposition. ACS Appl. Mater. Interfaces 9, 22676–22684 (2017)10.1021/acsami.7b04637 ↗
42. Maeng, W.J., Choi, D.W., Park, J., Park, J.S.: Indium oxide thin film prepared by low temperature atomic layer deposition using liquid precursors and ozone oxidant. J. Alloys Compd. 649, 216–221 (2015)10.1016/j.jallcom.2015.07.150 ↗
43. Lee, K.H., Lee, S.H., Cho, S.J., Hwang, C.S., Park, S.H.K.: Improving the electrical performance of vertical thin-film transistor by engineering its back-channel interface. Microelectron. Eng. 253, 111676 (2021)10.1016/j.mee.2021.111676 ↗
44. Hamblen, D.P., Cha-Lin, A.: Angular etching correlations from RIE: application to VLSI fabrication and process modeling. J. Electrochem. Soc. 135, 1816 (1988)10.1149/1.2096138 ↗
45. Kim, J.S., Kim, D.H., Cho, S.I., Lee, S.H., Jeong, W.S., Park, S.H.K.: Channel-shortening effect suppression of a high-mobility self-aligned oxide TFT using trench structure. IEEE Electron Device Lett. 42, 1798–1801 (2021)10.1109/LED.2021.3125146 ↗
46. Bae, S.H., Ryoo, H.J., Yang, J.H., Kim, Y.H., Hwang, C.S., Yoon, S.M.: Influence of reduction in effective channel length on device operations of In–Ga–Zn–O thin-film transistors with variations in channel compositions. IEEE Trans. Electron Devices 68, 6159–6165 (2021)10.1109/TED.2021.3117188 ↗
47. Kim, W.S., Moon, Y.K., Kim, K.T., Lee, J.H., Park, J.W.: An investigation of contact resistance between metal electrodes and amorphous gallium–indium–zinc oxide (a-GIZO) thin-film transistors. Thin Solid Films 518, 6357–6360 (2010)10.1016/j.tsf.2010.02.044 ↗
48. Park, J.C., Kim, C.J., Kim, S.I., Song, I.H., Kim, S.W., Kang, D.H., Lim, H., Yin, H., Jung, R.J., Lee, E.H.: Source/drain series-resistance effects in amorphous gallium–indium zinc-oxide thin film transistors. IEEE Electron Device Lett. 29, 879–881 (2008)10.1109/LED.2008.2000815 ↗