Effect of applied bias voltage on grain boundary potential barrier height (Φ b ) in semiconductor nanocrystals

Carrier transport through electrically active grain boundaries was studied under biased condition using impedance spectroscopy in the frequency range 1 Hz to 1 MHz for a model system nanocrystalline CuSCN. Since, grain boundaries of semiconductors contain defects which often trap charge carriers and cause to form a potential barrier around them also plays a crucial role in the electrical properties of nanomaterials. The influence of bias voltage on relaxation times of grain (τg) and grain boundary (τgb) for our wet chemically prepared nanocrystalline CuSCN was estimated at a periodic increment of 0.35 V from 0 V to −4.2 V. In the static case with no applied bias voltage the grain boundary potential barrier height was found to be 0.144 eV. During each periodic increment of applied bias voltages, both the grain and grain boundary relaxation times are decreases it gives direct and unambiguous evidence on the suppression of grain boundary potential barrier height (Φb).