Effect of Electrons Trapping/De-Trapping at Si-SiO2Interface on Two-State Current in MOS(p) Structure with Ultra-Thin SiO2by Anodization
Source abstract
Abstract
The phenomenon of two-state inversion gate current of metal-oxide-semiconductor device with p-type substrate (Al/SiO2/p-Si structure using an anodized SiO2 layer) at VG>0 was investigated. Different amounts of electrons are trapped/de-trapped at Si-SiO2 interface after exerting different set/reset stressing voltages over different set/reset time. And the electron trapping/de-trapping at the Si-SiO2 interface near the conduction band is thus proposed to rationalize the decreased/revertible gate current (Iset /Ireset) at VG>0. In particular, the Iset increases with the decreasing amount of trapped electrons. Furthermore, a specific voltage of sustainable voltage is proposed to investigate the filling condition of the Si-SiO2 interface traps in this paper. This simple and fully complementary metal-oxide-semiconductor compatible structure might have the potential application in memory devices.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis · Advancements in Semiconductor Devices and Circuit Design
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
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