Optimization for Device Figure of Merit of Ferroelectric Tunnel FET using Genetic Algorithm

Tunnel FET is a gate-controlled, field effect transistor, followed band to band tunneling (BTBT) transport of charge carriers, having low subthreshold swing (SS < 60 Mv decade⁻¹|T = 300 K). With tunnel FET, low-I_ON is a built-in problem, that limits its universal adaptability high-speed low-power uses. To overcome, this limitation of tunnel FET, a conventional double gate TFET has acquired for analysis having ferroelectric (BaTiO₃)/HfO₂ gate materials and source/channel region with Si_1−xGe_x/Si semiconductor channel composition.The present device design techniques enhanced the I_ON and put down the subthreshold swing(SS). The analysis results by using the Silvaco simulator shows improvement in switching current(I_ON) approximately ∼10³ times better than conventional DGTFET,without affecting the I_OFF. Ultimately the change in I_ON∼order of 10⁻⁸ A μm⁻¹ to 10⁻⁵ A μ has been measured for V_DS ∼ 0.5 V at room temperature. The I_OFF ( ∼10⁻²⁰ A μm⁻¹) has been measured. In addition to this, first time genetic algorithm has been used for the optimization of ferroelectric tunnel FET (Fe-Tunnel FET) device design parameters like a subthreshold swing (SS), ambipolar current (I_amb) and I_ONby using device deign parameters, doping (N_S, N_D), dielectric (ε_OX) and work function (WF).The research conclusion shows that Fe-Tunnel can play in lead backgroundfor super low power applications in advanced VLSI circuit and system.