Monolithic 3D integration as a pathway to energy-efficient computing and beyond: From materials and devices to architectures and chips
Source abstract
Abstract
As emerging technologies like artificial intelligence (AI) and big data continue to evolve, the demand for high-performance computing (HPC) has been increasing, driving the development of computing chips towards greater energy efficiency and multifunctionality. Monolithic 3D integration (M3D) is poised to be a key enabling technology, by vertically stacking multiple functional layers made of backend-of-the-line (BEOL)-compatible devices on top of Si circuits and interconnecting them with high-density interlayer vias (ILVs). Currently, contenders for functional materials and devices in M3D include carbon nanotubes, two-dimensional (2D) materials, oxide semiconductors and a variety of emerging memories, such as resistive random-access memory (RRAM). This article first discusses the key properties and latest research developments of those materials and their device applications. As a representative example, we then review the recent progress on RRAM-based M3D architectures that integrate memory, computing, and other functional elements to facilitate computing-in-memory (CIM). Finally, we further discuss the opportunities and challenges of M3D as a promising pathway to energy-efficient computing.
Source: expertdata · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advanced Memory and Neural Computing · Semiconductor materials and devices · 3D IC and TSV technologies
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (100+)
Show source-provided references
1. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm10.1109/16.887014 ↗
2. The End of Moore’s Law: A New Beginning for Information Technology10.1109/MCSE.2017.29 ↗
3. The chemistry of functional nanomaterials10.1039/c3cs90011h ↗
4. Challenges and opportunities in low-dimensional thermoelectric nanomaterials10.1016/j.mattod.2023.04.021 ↗
5. Strain Engineering of Low-Dimensional Materials for Emerging Quantum Phenomena and Functionalities10.1002/adma.202107362 ↗
6. Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse10.1109/TVLSI.2020.3015494 ↗
7. Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing10.1109/MM.2020.3045564 ↗
8. S. Naffziger, K. Lepak, M. Paraschou, M. Subramony, 2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products, in: 2020 IEEE International Solid- State Circuits Conference - (ISSCC), IEEE, San Francisco, CA, USA, 2020: pp. 44–45. .10.1109/ISSCC19947.2020.9063103 ↗
9. Y. Kagawa, N. Fujii, K. Aoyagi, Y. Kobayashi, S. Nishi, N. Todaka, S. Takeshita, J. Taura, H. Takahashi, Y. Nishimura, K. Tatani, M. Kawamura, H. Nakayama, T. Nagano, K. Ohno, H. Iwamoto, S. Kadomura, T. Hirayama, Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding, in: 2016 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2016: p. 8.4.1-8.4.4. https://doi.org/10.1109/IEDM.2016.7838375.10.1109/IEDM.2016.7838375 ↗
10. C.-C. Hsiao, H.-C. Fu, C.-W. Chiang, O.-H. Lee, T.-Y.O. Yang, H.-H. Chang, Feasibility Study of Nanotwinned Copper and Adhesive Hybrid Bonding for Heterogeneous Integration, in: 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), IEEE, San Diego, CA, USA, 2021: pp. 445–450. https://doi.org/10.1109/ECTC32696.2021.00081.10.1109/ECTC32696.2021.00081 ↗
11. Reliability of the hybrid bonding level using submicrometric bonding pads10.1016/j.microrel.2023.115189 ↗
12. International Roadmap for Devices and Systems (IRDSTM) 2022 Edition - IEEE IRDSTM. https://irds.ieee.org/editions/2022 (accessed December 10, 2023).
13. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip10.1038/nature22994 ↗
14. Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects
15. R. Fox, O. Hinsinger, E. Richard, E. Sabouret, T. Berger, C. Goldberg, A. Humbert, G. Imbert, P. Brun, E. Ollier, C. Maurice, M. Guillermet, C. Monget, V. Plantier, H. Bono, M. Zaleski, M. Mellier, J.-P. Jacquemin, J. Flake, B.G. Sharma, L. Broussous, A. Farcy, V. Arnal, R. Gonella, S. Maubert, V. Girault, P. Vannier, D. Reber, A. Schussler, J. Mueller, W. Besling, High performance k=2.5 ULK backend solution using an improved TFHM architecture, extendible to the 45nm technology node, in: IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., IEEE, Tempe, Arizon, USA, 2005: pp. 81–84. https://doi.org/10.1109/IEDM.2005.1609272.10.1109/IEDM.2005.1609272 ↗
16. Band Structure, Phonon Scattering, and the Performance Limit of Single-Walled Carbon Nanotube Transistors10.1103/PhysRevLett.95.146805 ↗
17. W. Hwang, W. Wan, S. Mitra, H.-S.P. Wong, Coming Up N3XT, After 2D Scaling of Si CMOS, in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Florence, 2018: pp. 1–5. .10.1109/ISCAS.2018.8351756 ↗
18. Evaluation of Field-Effect Mobility and Contact Resistance of Transistors That Use Solution-Processed Single-Walled Carbon Nanotubes10.1021/nn302185d ↗
19. Carbon Nanotube Robust Digital VLSI10.1109/TCAD.2012.2187527 ↗
20. Carbon nanotube computer10.1038/nature12502 ↗
21. T. Srimani, A.C. Yu, R.M. Radway, D.T. Rich, M. Nelson, S. Wong, D. Murphy, S. Fuller, G. Hills, S. Mitra, M.M. Shulaker, Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM, in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2023: pp. 1–2. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185414.10.23919/VLSITechnologyandCir57934.2023.10185414 ↗
22. T. Srimani, R.M. Radway, J. Kim, K. Prabhu, D. Rich, C. Gilardi, P. Raina, M. Shulaker, S.K. Lim, S. Mitra, Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits, in: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Antwerp, Belgium, 2023: pp. 1–6. https://doi.org/10.23919/DATE56975.2023.10137051.10.23919/DATE56975.2023.10137051 ↗
23. Y. Zhang, Y. Li, J. Tang, N. Gao, L. Gao, H. Xu, R. An, Q. Qin, Z. Liu, D. Wu, B. Gao, H. Qian, H. Wu, 3D Stackable CNTFET/RRAM 1T1R Array with CNT CMOS Peripheral Circuits as BEOL Buffer Macro for Monolithic 3D Integration with Analog RRAM-based Computing-In-Memory, in: 2023 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2023: pp. 1–4. https://doi.org/10.1109/IEDM45741.2023.10413717.10.1109/IEDM45741.2023.10413717 ↗
24. Y. Li, J. Tang, B. Gao, J. Yao, Y. Xi, Y. Li, T. Li, Y. Zhou, Z. Liu, Q. Zhang, S. Qiu, Q. Li, H. Qian, H. Wu, Monolithic 3D Integration of Logic, Memory and Computing-In-Memory for One-Shot Learning, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 21.5.1-21.5.4. https://doi.org/10.1109/IEDM19574.2021.9720534.10.1109/IEDM19574.2021.9720534 ↗
25. Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning10.1038/s41467-023-42981-1 ↗
26. Carbon Nanotube Based Radio Frequency Transistors for K-Band Amplifiers10.1021/acsami.1c07782 ↗
27. Radiofrequency transistors based on aligned carbon nanotube arrays10.1038/s41928-021-00594-w ↗
28. M.-Y. Li, C.-H. Hsu, S.-W. Shen, A.-S. Chou, Y.C. Lin, C.-P. Chuu, N. Yang, S.-A. Chou, L.-Y. Huang, C.-C. Cheng, W.-Y. Woon, S. Liao, C.-I. Wu, L.-J. Li, I. Radu, H.-S.P. Wong, H. Wang, Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS 2 Transistor, in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2022: pp. 290–291. .10.1109/VLSITechnologyandCir46769.2022.9830376 ↗
29. S.-X. Guan, T.H. Yang, C.-H. Yang, C.-J. Hong, B.-W. Liang, K.B. Simbulan, J.-H. Chen, C.-J. Su, K.-S. Li, Y.-L. Zhong, L.-J. Li, Y.-W. Lan, Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET, Npj 2D Mater Appl 7 (2023) 9. https://doi.org/10.1038/s41699-023-00371-7.10.1038/s41699-023-00371-7 ↗
30. Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors10.1038/s41565-023-01399-y ↗
31. An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning10.1038/s41565-023-01343-0 ↗
32. Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions10.1038/s41563-023-01704-z ↗
33. Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform10.1038/s41565-023-01375-6 ↗
34. Highly reproducible van der Waals integration of two-dimensional electronics on the wafer scale10.1038/s41565-023-01342-1 ↗
35. Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In2Se3 for stacked in-memory computing array10.1038/s41467-023-41991-3 ↗
36. Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory10.1038/s41467-023-41736-2 ↗
37. W. Meng, F. Xu, X. Shen, T. Tao, Z. Yu, K. Wen, J. Wang, F. Qin, X. Tu, J. Ning, D. Wang, Y. Zheng, B. Liu, R. Zhang, Y. Shi, X. Wang, Monolithic 3D $\mu$-LED displays through BEOL integration of large-area MoS 2 TFT matrix, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 9.4.1-9.4.4. https://doi.org/10.1109/IEDM19574.2021.9720703.10.1109/IEDM19574.2021.9720703 ↗
38. Three-dimensional monolithic micro-LED display driven by atomically thin transistor matrix10.1038/s41565-021-00966-5 ↗
39. U. Chand, Z. Fang, C. Chun-Kuei, Y. Luo, H. Veluri, M. Sivan, L.J. Feng, S.-H. Tsai, S. Chakraborty, E. Zamburg, A.V.-Y. Thean, 2-kbit Array of 3-D Monolithically-stacked IGZO FETs with Low SS-64mV/dec, Ultra-low-leakage, Competitive µ-57 cm2/V-s Performance and Novel nMOS-Only Circuit Demonstration, in: 2021 Symposium on VLSI Technology, IEEE, Kyoto, Japan, 2021: p. 10.2.1-10.2.2.
40. A. Belmonte, H. Oh, S. Subhechha, N. Rassoul, H. Hody, H. Dekkers, R. Delhougne, L. Ricotti, K. Banerjee, A. Chasin, M.J. Van Setten, H. Puliyalil, M. Pak, L. Teugels, D. Tsvetanova, K. Vandersmissen, S. Kundu, J. Heijlen, D. Batuk, J. Geypen, L. Goux, G.S. Kar, Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 10 3 s retention, >10 11 cycles endurance and L g scalability down to 14nm, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 10.6.1-10.6.4. .10.1109/IEDM19574.2021.9720596 ↗
41. H. Baba, S. Ohshita, T. Hamada, Y. Ando, R. Hodo, T. Ono, T. Hirose, Y. Kurokawa, T. Murakawa, H. Kunitake, T. Nakura, M. Kobayashi, H. Yoshida, M.-C. Chen, M.-H. Liao, S.-Z. Chang, S. Yamazaki, Novel Analog in-Memory Compute with > 1 nA Current/Cell and 143.9 TOPS/W Enabled by Monolithic Normally-off Zn-rich CAAC-IGZO FET-on-Si CMOS Technology, in: 2021 IEEE International Electron Devices Meeting (IEDM), 2021: p. 21.2.1-21.2.4. https://doi.org/10.1109/IEDM19574.2021.9721312.10.1109/IEDM19574.2021.9721312 ↗
42. J. Liu, C. Sun, W. Tang, Z. Zheng, Y. Liu, H. Yang, C. Jiang, K. Ni, X. Gong, X. Li, Low-Power and Scalable Retention-Enhanced IGZO TFT eDRAM-Based Charge-Domain Computing, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 21.1.1-21.1.4. .10.1109/IEDM19574.2021.9720576 ↗
43. C. Chen, X. Duan, G. Yang, C. Lu, D. Geng, L. Li, M. Liu, Inter-Layer Dielectric Engineering for Monolithic Stacking 4F 2 -2 T0C DRAM with Channel-All-Around (CAA) IGZO FET to Achieve Good Reliability (>10 4 s Bias Stress, >10 12 Cycles Endurance), in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 26.5.1-26.5.4. https://doi.org/10.1109/IEDM45625.2022.10019502.10.1109/IEDM45625.2022.10019502 ↗
44. W. Lu, Z. Zhu, K. Chen, M. Liu, B.-M. Kang, X. Duan, J. Niu, F. Liao, W. Dan, X.-S. Wu, J. Son, D.-Y. Xiao, G.-L. Wang, A. Yoo, K.-Y. Cao, D. Geng, N. Lu, G. Yang, C. Zhao, L. Li, M. Liu, First Demonstration of Dual-Gate IGZO 2T0C DRAM with Novel Read Operation, One Bit Line in Single Cell, I ON =1500 μA/μm@V DS =1V and Retention Time>300s, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 26.4.1-26.4.4. .10.1109/IEDM45625.2022.10019488 ↗
45. True Nonvolatile High-Speed DRAM Cells Using Tailored Ultrathin IGZO10.1002/adma.202210554 ↗
46. Z. Zhou, L. Jiao, Q. Kong, Z. Zheng, K. Han, Y. Chen, C. Sun, B.-Y. Nguyen, X. Gong, Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F 2 High-Density Integration, in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2023: pp. 1–2. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185243.10.23919/VLSITechnologyandCir57934.2023.10185243 ↗
47. X.-R. Yu, M.-H. Chuang, S.-W. Chang, W.-H. Chang, T.-C. Hong, C.-H. Chiang, W.-H. Lu, C.-Y. Yang, W.-J. Chen, J.-H. Lin, P.-H. Wu, T.-C. Sun, S. Kola, Y.-S. Yang, Y. Da, P.-J. Sung, C.-T. Wu, T.-C. Cho, G.-L. Luo, K.-H. Kao, M.-H. Chiang, W.C.-Y. Ma, C.-J. Su, T.-S. Chao, T. Maeda, S. Samukawa, Y. Li, Y.-J. Lee, W.-F. Wu, J.-H. Tarng, Y.-H. Wang, Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 20.5.1-20.5.4. https://doi.org/10.1109/IEDM45625.2022.10019507.10.1109/IEDM45625.2022.10019507 ↗
48. Y. Du, J. Tang, Y. Li, Y. Xi, B. Gao, H. Qian, H. Wu, Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture, in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023: pp. 1–2. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185221.10.23919/VLSITechnologyandCir57934.2023.10185221 ↗
49. J. Wu, Mobility-enhanced FET and Wakeup-free Ferroelectric Capacitor Enabled by Sn-doped InGaZnO for 3D Embedded RAM Application, in: 2021 Symposium on VLSI Technology, IEEE, Kyoto, Japan, 2021: p. 6.2.1-6.2.2.
50. C.-K. Chen, Z. Fang, S. Hooda, M. Lal, U. Chand, Z. Xu, J. Pan, S.-H. Tsai, E. Zamburg, A.V.-Y. Thean, First Demonstration of Ultra-low D it Top-Gated Ferroelectric Oxide-Semiconductor Memtransistor with Record Performance by Channel Defect Self-Compensation Effect for BEOL-Compatible Non-Volatile Logic Switch, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 6.1.1-6.1.4. .10.1109/IEDM45625.2022.10019440 ↗
51. Y. Qin, C. Lu, Z. Yu, Z. Yao, F. Wu, D. Dong, X. Zhao, G. Xu, Y. Zhang, S. Long, L. Li, M. Liu, First Demonstration of High-Sensitivity (NEP<1fW•Hz -1/2) Back-Illuminated Active-Matrix Deep UV Image Sensor by Monolithic Integration of Ga 2 O 3 Photodetectors and Oxide Thin-Film-Transistors, in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2022: pp. 345–346. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830520.10.1109/VLSITechnologyandCir46769.2022.9830520 ↗
52. Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing
53. M. Si, Z. Lin, Z. Chen, P.D. Ye, First Demonstration of Atomic-Layer-Deposited BEOL-Compatible In2O3 3D Fin Transistors and Integrated Circuits: High Mobility of 113 cm2/V⋅s, Maximum Drain Current of 2.5 mA/m and Maximum Voltage Gain of 38 V/V in In2O3 Inverter, in: 2021 Symposium on VLSI Technology, IEEE, Kyoto, Japan, 2021: p. 2.4.1-2.4.2.
54. Scaled indium oxide transistors fabricated using atomic layer deposition10.1038/s41928-022-00718-w ↗
55. Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors10.1038/s41467-023-41041-y ↗
56. Z. Lin, M. Si, P.D. Ye, Ultra-Fast Operation of BEOL-Compatible Atomic-Layer-Deposited In 2 O 3 Fe-FETs: Achieving Memory Performance Enhancement with Memory Window of 2.5 V and High Endurance > 10 9 Cycles without V T Drift Penalty, in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2022: pp. 1–2. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830156.10.1109/VLSITechnologyandCir46769.2022.9830156 ↗
57. Z. Lin, M. Si, Y.-C. Luo, X. Lyu, A. Charnas, Z. Chen, Z. Yu, W. Tsai, P.C. McIntyre, R. Kanjolia, M. Moinpour, S. Yu, P.D. Ye, High-Peformance BEOL-Compatible Atomic-Layer-Deposited In 2 O 3 Fe-FETs Enabled by Channel Length Scaling down to 7 nm: Achieving Performance Enhancement with Large Memory Window of 2.2 V, Long Retention > 10 years and High Endurance > 10 8 Cycles, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 17.4.1-17.4.4. https://doi.org/10.1109/IEDM19574.2021.9720652.10.1109/IEDM19574.2021.9720652 ↗
58. D. Zheng, A. Charnas, J.-Y. Lin, J. Anderson, D. Weinstein, P.D. Ye, Ultrathin Atomic-Layer-Deposited In 2 O 3 Radio-Frequency Transistors with Record High f T of 36 GHz and BEOL Compatibility, in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2023: pp. 1–2. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185331.10.23919/VLSITechnologyandCir57934.2023.10185331 ↗
59. Capacitorless DRAM Cells Based on High-Performance Indium-Tin-Oxide Transistors With Record Data Retention and Reduced Write Latency10.1109/LED.2022.3225263 ↗
60. J. Park, D.-M. Geum, W. Baek, J. Shieh, S. Kim, Monolithic 3D sequential integration realizing 1600-PPI red micro-LED display on Si CMOS driver IC, in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2022: pp. 383–384. .10.1109/VLSITechnologyandCir46769.2022.9830425 ↗
61. K.A. Aabrar, J. Gomez, S.G. Kirtania, M.S. Jose, Y. Luo, P.G. Ravikumar, P.V. Ravindran, H. Ye, S. Banerjee, S. Dutta, A.I. Khan, S. Yu, S. Datta, BEOL Compatible Superlattice FerroFET-based High Precision Analog Weight Cell with Superior Linearity and Symmetry, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 19.6.1-19.6.4. .10.1109/IEDM19574.2021.9720713 ↗
62. Y. Luo, S. Dutta, A. Kaul, S. Lim, M. Bakir, S. Datta, S. Yu, Monolithic 3D Compute-in-Memory Accelerator with BEOL Transistor based Reconfigurable Interconnect, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 25.3.1-25.3.4. .10.1109/IEDM19574.2021.9720690 ↗
63. A. Khanna, H. Ye, Y. Luo, G. Bajpai, M.S. Jose, W. Chakraborty, S. Yu, P. Fay, S. Datta, BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators, in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2022: pp. 240–241. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830498.10.1109/VLSITechnologyandCir46769.2022.9830498 ↗
64. S.G. Kirtania, K.A. Aabrar, A.I. Khan, S. Yu, S. Datta, Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance, in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2023: pp. 1–2. .10.23919/VLSITechnologyandCir57934.2023.10185382 ↗
65. Z. Zhao, J. Gomez, H. Ye, M. Imani, X. Yin, S. Deng, B. Melanson, J. Zhang, X. Gong, A. Abusleme, S. Datta, K. Ni, Computational Associative Memory Based on Monolithically Integrated Metal-Oxide Thin Film Transistors for Update-Frequent Search Applications, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 37.6.1-37.6.4. https://doi.org/10.1109/IEDM19574.2021.9720705.10.1109/IEDM19574.2021.9720705 ↗
66. S. Dutta, A. Khanna, H. Ye, M.M. Sharifi, A. Kazemi, M.S. Jose, K.A. Aabrar, J.G. Mir, M. Niemer, X.S. Hu, S. Datta, Lifelong Learning with Monolithic 3D Ferroelectric Ternary Content-Addressable Memory, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: pp. 1–4. .10.1109/IEDM19574.2021.9720495 ↗
67. Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics10.1126/science.aba5980 ↗
68. Monolithic three-dimensional integration of aligned carbon nanotube transistors for high-performance integrated circuits10.1002/inf2.12420 ↗
69. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes10.1038/nnano.2016.44 ↗
70. Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs10.1126/sciadv.1601240 ↗
71. Charge transport in semiconducting carbon nanotube networks10.1063/5.0065730 ↗
72. Fabrication of carbon nanotube field-effect transistors in commercial silicon manufacturing facilities10.1038/s41928-020-0419-7 ↗
73. T. Srimani, G. Hills, M. Bishop, C. Lau, P. Kanhaiya, R. Ho, A. Amer, M. Chao, A. Yu, A. Wright, A. Ratkovich, D. Aguilar, A. Bramer, C. Cecman, A. Chov, G. Clark, G. Michaelson, M. Johnson, K. Kelley, P. Manos, K. Mi, U. Suriono, S. Vuntangboon, H. Xue, J. Humes, S. Soares, B. Jones, S. Burack, Arvind, A. Chandrakasan, B. Ferguson, M. Nelson, M.M. Shulaker, Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 nm node, in: 2020 IEEE Symposium on VLSI Technology, IEEE, Honolulu, HI, USA, 2020: pp. 1–2. https://doi.org/10.1109/VLSITechnology18217.2020.9265083.10.1109/VLSITechnology18217.2020.9265083 ↗
74. Modern microprocessor built from complementary carbon nanotube transistors10.1038/s41586-019-1493-8 ↗
75. T. Srimani, A.C. Yu, B. Benton, M. Nelson, M.M. Shulaker, Lift-off-Free Complementary Carbon Nanotube FETs Fabricated With Conventional Processing in a Silicon Foundry, in: 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), IEEE, Hsinchu, Taiwan, 2022: pp. 1–2. .10.1109/VLSI-TSA54299.2022.9771013 ↗
76. Foundry Integration of Carbon Nanotube FETs With 320 nm Contacted Gate Pitch Using New Lift-Off-Free Process10.1109/LED.2022.3144936 ↗
77. Flexible CMOS integrated circuits based on carbon nanotubes with sub-10 ns stage delays10.1038/s41928-018-0038-8 ↗
78. J. Tang, Q. Cao, D.B. Farmer, G. Tulevski, S.-J. Han, Carbon nanotube complementary logic with low-temperature processed end-bonded metal contacts, in: 2016 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2016: p. 5.1.1-5.1.4. https://doi.org/10.1109/IEDM.2016.7838350.10.1109/IEDM.2016.7838350 ↗
79. K. Maxey, C.H. Naylor, K.P. O’Brien, A. Penumatcha, A. Oni, C. Mokhtarzadeh, C.J. Dorow, C. Rogan, B. Holybee, T. Tronic, D. Adams, N. Arefin, A. Sen Gupta, C.-C. Lin, T. Zhong, S. Lee, A. Kitamura, R. Bristol, S.B. Clendenning, U. Avci, M. Metz, 300 mm MOCVD 2D CMOS Materials for More (Than) Moore Scaling, in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2022: pp. 419–420. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830457.10.1109/VLSITechnologyandCir46769.2022.9830457 ↗
80. Three-dimensional integration of two-dimensional field-effect transistors10.1038/s41586-023-06860-5 ↗
81. Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing10.1038/s41467-022-30519-w ↗
82. Active pixel sensor matrix based on monolayer MoS2 phototransistor array10.1038/s41563-022-01398-9 ↗
83. Hardware implementation of Bayesian network based on two-dimensional memtransistors10.1038/s41467-022-33053-x ↗
84. Scaled Atomic-Layer-Deposited Indium Oxide Nanometer Transistors With Maximum Drain Current Exceeding 2 A/mm at Drain Voltage of 0.7 V10.1109/LED.2020.3043430 ↗
85. Nanometre-thin indium tin oxide for advanced high-performance electronics10.1038/s41563-019-0455-8 ↗
86. W. Chakraborty, B. Grisafe, H. Ye, I. Lightcap, K. Ni, S. Datta, BEOL Compatible Dual-Gate Ultra Thin-Body W-Doped Indium-Oxide Transistor with Ion = 370μA/μm, SS = 73mV/dec and Ion /Ioff Ratio > 4×109, in: 2020 IEEE Symposium on VLSI Technology, IEEE, Honolulu, HI, USA, 2020: pp. 1–2. https://doi.org/10.1109/VLSITechnology18217.2020.9265064.10.1109/VLSITechnology18217.2020.9265064 ↗
87. D. Zheng, A. Charnas, J. Anderson, H. Dou, Z. Hu, Z. Lin, Z. Zhang, J. Zhang, P.-Y. Liao, M. Si, H. Wang, D. Weinstein, P.D. Ye, First Demonstration of BEOL-Compatible Ultrathin AtomicLayer-Deposited InZnO Transistors with GHz Operation and Record High Bias-Stress Stability, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 4.3.1-4.3.4. https://doi.org/10.1109/IEDM45625.2022.10019452.10.1109/IEDM45625.2022.10019452 ↗
88. Y.-K. Liang, J.-Y. Zheng, Y.-L. Lin, W.-L. Li, Y.-C. Lu, D.-R. Hsieh, L.-C. Peng, T.-T. Chou, C.-C. Kei, C.-C. Lu, H.-Y. Huang, Y.-C. Tseng, T.-S. Chao, E.Y. Chang, C.-H. Lin, Aggressively Scaled Atomic Layer Deposited Amorphous InZnO x Thin Film Transistor Exhibiting Prominent Short Channel Characteristics (SS= 69 mV/dec.; DIBL = 27.8 mV/V) and High G m (802 μS/μm at V DS = 2V), in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2023: pp. 1–2. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185343.10.23919/VLSITechnologyandCir57934.2023.10185343 ↗
89. Q. Li, C. Gu, S. Zhu, Q. Hu, W. Zhao, X. Li, R. Huang, Y. Wu, BEOL-Compatible High-Performance a-IGZO Transistors with Record high I ds,max = 1207 μA/μm and on-off ratio exceeding 10 11 at Vds = 1V, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 2.7.1-2.7.4. .10.1109/IEDM45625.2022.10019448 ↗
90. X. Duan, K. Huang, J. Feng, J. Niu, H. Qin, S. Yin, G. Jiao, D. Leonelli, X. Zhao, W. Jing, Z. Wang, Q. Chen, X. Chuai, C. Lu, W. Wang, G. Yang, D. Geng, L. Li, M. Liu, Novel Vertical Channel-All-Around(CAA) IGZO FETs for $2\mathrm{T}0\mathrm{C}$ DRAM with High Density beyond 4F2 by Monolithic Stacking, in: 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021: p. 10.5.1-10.5.4. https://doi.org/10.1109/IEDM19574.2021.9720682.10.1109/IEDM19574.2021.9720682 ↗
91. U. Chand, M.M. Sabry Aly, M. Lal, C. Chun-Kuei, S. Hooda, S.-H. Tsai, Z. Fang, H. Veluri, A. Voon-Yew Thean, Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm I ON at V DS 1V, High µ-84 cm 2 /V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing, in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2022: pp. 326–327. .10.1109/VLSITechnologyandCir46769.2022.9830250 ↗
92. CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor10.1038/s41467-023-41868-5 ↗
93. Progress, Challenges, and Opportunities in Oxide Semiconductor Devices: A Key Building Block for Applications Ranging from Display Backplanes to 3D Integrated Semiconductor Chips10.1002/adma.202204663 ↗
94. P.-Y. Liao, S. Alajlouni, Z. Zhang, Z. Lin, M. Si, J. Noh, T.I. Feygelson, M.J. Tadjer, A. Shakouri, P.D. Ye, Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD In2O3 FETs on Various Thermally Conductive Substrates Including Diamond, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 12.4.1-12.4.4. https://doi.org/10.1109/IEDM45625.2022.10019438.10.1109/IEDM45625.2022.10019438 ↗
95. . Zhang, Z. Lin, A. Charnas, H. Dou, Z. Shang, J. Zhang, M. Si, H. Wang, M.A. Alam, P.D. Ye, Reliability of Atomic-Layer-Deposited Gate-All-Around In 2 O 3 Nano-Ribbon Transistors with Ultra-High Drain Currents, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 30.3.1-30.3.4. .10.1109/IEDM45625.2022.10019494 ↗
96. Enhancement-Mode Atomic-Layer-Deposited In 2 O 3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing and Stability in Hydrogen Environment10.1109/TED.2021.3053229 ↗
97. Z. Zhang, Z. Lin, C. Niu, M. Si, M.A. Alam, P.D. Ye, Ultrahigh Bias Stability of ALD In 2 O 3 FETs Enabled by High Temperature O 2 Annealing, in: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2023: pp. 1–2. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185292.10.23919/VLSITechnologyandCir57934.2023.10185292 ↗
98. Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution10.1126/sciadv.1602640 ↗
99. Y. Hu, H. Ye, K.A. Aabrar, S.G. Kirtania, W. Chakraborty, S. Datta, K. Cho, Theoretical and Empirical Insight into Dopant, Mobility and Defect States in W Doped Amorphous In 2 O 3 for High-Performance Enhancement Mode BEOL Transistors, in: 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022: p. 8.5.1-8.5.4. https://doi.org/10.1109/IEDM45625.2022.10019366.10.1109/IEDM45625.2022.10019366 ↗
100. Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors10.1038/nature03090 ↗