Scalable Ternary Logic Device Based on TeOx/IGTO Heterojunction Transistor

Abstract In today's era of rapid data proliferation, interconnect bottlenecks pose major challenges for conventional binary computing systems. These challenges encompass not only managing vast data volumes but also the substantial power consumption associated with data processing. To address these limitations, ternary logic systems have attracted considerable interest due to their capability to process information at higher densities within the same physical footprint compared to binary logic systems. Here, scalable ternary logic devices are demonstrated that are fully compatible with complementary‐metal‐oxide‐semiconductor (CMOS) technology. These devices are based on p‐n heterojunction thin‐film transistors (TFTs) composed of InGaSnO and TeO _X , fabricated using a low processing temperature of 150 °C. The resulting heterojunction TFTs exhibit highly reproducible negative differential transconductance behavior with a peak‐to‐valley current ratio exceeding 10 ³ . By monolithically integrating these high‐performance p‐n heterojunction TFTs with p‐channel TeO _X TFTs, ternary logic devices are demonstrated. The optimized device architecture facilitates sophisticated transconductance matching, enabling the realization of a stable intermediate logic state. The use of low‐temperature, CMOS‐compatible processes ensures scalability and industrial compatibility, highlighting oxide semiconductors as a compelling material platform for next‐generation ternary logic technologies. This work is a pivotal advancement toward energy‐efficient, high‐density ternary systems, paving the way for transformative computational paradigms.