One Micrometer Channel Length, Coplanar Polycrystalline InGaO Thin Film Transistors Exhibiting 85 cm² V⁻¹ s⁻¹ Mobility and Excellent Bias Stabilities by Using Offset Engineering

Abstract The effect of N+ resistivity in the offset region, for ≈1 µm channel length coplanar, polycrystalline InGaO (PC‐IGO) thin‐film transistors (TFTs) is studied. The room temperature deposited amorphous IGO is solid phase crystallized at 450 °C. The PC‐IGO TFT exhibits a maximum effective field‐effect mobility (µ_FE) of ≈86.69 cm² V⁻¹ s⁻¹, a threshold voltage of ≈1.5 V, and a subthreshold swing of ≈300 mV decade⁻¹, with remarkable stability under bias and temperature stress. The offset length (L_off) is varied from 1 to 3 µm and their electrical performances are analyzed. Upon increasing the L_off from 1 to 3 µm, the on current (I_on) and the µ_FE drops from 50.31 to 17.72 µA and 85.40 to 67.64 cm² V⁻¹ s⁻¹, respectively, which can be attributed to a greater voltage drop in the L_off, resulting in the reduction of effective V_DS applied to the channel. Technology computer‐aided design simulations shows that at the sheet resistance of 14.5 Ω sq⁻¹. in the N+ offset region, the I_on dependency disappears with the change in L_off, which is attributed to the negligible voltage drop. These results provide valuable insight into optimizing N+ doping, for high‐performance, short‐channel coplanar oxide TFTs.