High mechanical and electrical reliability of bottom-gate microcrystalline silicon thin film transistors on polyimide substrate

Abstract Bottom-gate microcrystalline silicon thin film transistors (μc-Si:H TFTs) were fabricated by conventional 13.56 MHz RF plasma-enhanced chemical vapor deposition at 200 °C. In the high pressure depletion regime, the deposition rate of the μc-Si:H film is 24 nm/min and the amorphous incubation layer near the μc-Si:H/silicon nitride interface is unobvious. The crystalline fraction of μc-Si:H film with the thickness of 50 nm is 71%. From nano beam electron diffraction, the μc-Si:H film has a better crystalline order within a short-range lattice structure. The lattice parameter was measured to be 3.1 A, which reflecting the lattice plane has a (111) direction. Finally, the μc-Si:H film was used as the active layer in TFTs structure. The field effect mobility, subthreshold swing and the threshold voltage are 0.95 cm2/V, 0.85 V/dec. and 2.05 V, respectively. The output characteristic also shows no evidence of current crowing at low drain-source voltage (Vds), implying good contact properties achieved with the n+ a-Si:H source-drain ohmic contact layer. After 70 h 1 μA constant current stress, the threshold voltage shifts are 4.44 V and 0.42 V for the a-Si:H TFT and μc-Si:H TFT, respectively. The μc-Si:H thin film transistors show a better electrical stability than the amorphous silicon thin film transistors because of the lower defect density in the μc-Si:H film.