Electrical Modeling of Thin-Film Transistors

Abstract An overview of device physics-oriented electrical modeling of thin-film transistors (TFTs) is presented. Four specific models are considered: (i) square-law, (ii) 3-layer, (iii) comprehensive depletion-mode, and (iv) discrete trap. For each model, a functional assessment of model equations is undertaken in terms of independent and dependent variables, model parameters, physical operating parameters, and constraining inequalities in order to facilitate mapping of model equations into a corresponding equivalent circuit. Channel mobility and "subthreshold" current trends are elucidated. Finally, a conductance integral equation based on Shockley's gradual channel approximation is introduced and is employed in model development and device assessment. Keywords: thin-film transistordevice modelingsquare-law model3-layer modelcomprehensive depletion-mode modeldiscrete trap modelconductance integral equationchannel mobilityfringing current artifactsseries resistancetrapping ACKNOWLEDGMENTS This work was funded by the U.S. National Science Foundation under Grant No. DMR-0245386 and by an IGERT fellowship under Grant No. 0549503, by the Army Research Office under Contract No. MURI E-18-667-G3, and by the Hewlett-Packard Company, and by the Defense Advanced Research Projects Agency (MEMS/NEMS) Science and Technology Fundamentals.