Physics‐Based Compact Modeling of Advanced 3D Nanoscale Vertical NAND Flash Memory

ABSTRACT The increasing complexity of 3‐dimensional (3D) NAND flash memory necessitates advanced simulation frameworks to predict read behavior, program/erase (P/E) dynamics, and interactions between neighboring cells. We propose a unified compact model for Simulation Program with Integrated Circuit Emphasis (SPICE) that spans from the intrinsic unit cell to the full string and captures the electrostatic coupling with adjacent inhibit strings. The framework begins with a newly devised de‐embedding methodology that isolates the intrinsic cell characteristics from measured string current. These extracted behaviors are integrated into a compact model that reflects grain‐boundary‐induced mobility degradation in the polycrystalline‐silicon (poly‐Si) channel as well as its temperature dependence. To reproduce complex P/E transients, the model incorporates physics‐based voltage‐controlled current sources (VCCS), inter‐cell fringing capacitances, and a gate‐induced drain‐leakage (GIDL) capacitance network. By modeling not only the target string but also the channel‐potential evolution of neighboring inhibit strings, the framework captures key array‐level behaviors such as natural local self‐boosting (NLSB) and the down‐coupling phenomenon (DCP). The proposed unified model provides a powerful tool for reducing design uncertainty and enables accurate evaluation of design trade‐offs, including short‐channel effects from L _g /L _s scaling, bit‐line current (I _BL ) degradation with increased stacking, sensing‐margin variation, and the impact of gate‐stack engineering on P/E performance.