Influence of the Grain Boundaries and Intragrain Defects on the Performance of Poly‐Si Thin Film Transistors

The influence of grain boundaries and intragrain defects on poly‐Si thin‐film transistors (TFTs) was investigated by examining the crystallinity of poly‐Si films formed by solid phase crystallization (SPC) and excimer laser annealing (ELA), and the electrical characteristics of transistors fabricated on the poly‐Si films were examined. The increase in grain size by SPC improves field effect mobility (μ FE ) due to the increase in the emission current over the potential barrier height at the grain boundary. The decrease in intragrain defect densities by an oxide thinning process improves the μ FE , threshold voltage ( V th ) and subthreshold voltage swing ( S ). On the contrary, in spite of the small grain size of 800 Å, poly‐Si TFTs fabricated by ELA exhibit good characteristics with a high μ FE , low V th and low S , and good uniformity. It is found that since the realization of excellent performance and good uniformity in poly‐Si TFTs depends on a low trap state density at the grain boundaries and a low intragrain defect density, poly‐Si films formed by ELA are well suited for the application to poly‐Si TFT liquid crystal display with peripheral integrated circuits.