Response of as grown dislocation structure to temperature and stress treatment in multi-crystalline silicon

Abstract Dislocations and dislocation networks in multi-crystalline (mc) silicon wafers for photovoltaic applications act as minority carrier recombination centers and thus limit the efficiency of solar cells. The literature shows results for a massive dislocation reduction by applying an annealing procedure in combination with and without an impurity gettering step. In this work different kinds of annealing experiments with mc silicon samples were carried out at 1200 °C and 1365 °C for 1 h to 96 h under an applied stress of up to 4.2 MPa under pure inert or boron containing atmospheres. The results show clearly that, under the used process conditions, a dislocation reduction could not be observed via defect selective etching using different kinds of etchants. It was found, that it is essential to carefully select the etching solution as the electrical resistivity of the samples might change after a respective thermal treatment, such that the eventually still present dislocations will not be overseen.