Effects of localized gate stack parasitic charge on current-voltage characteristics of double-gate MOSFETs with high-permittivity dielectrics and Ge-channel

In this paper we investigate the effects of localized gate stack parasitic charges on the current-voltage characteristics of double-gate (DG) MOSFET with metal/high-permittivity/Ge-channel using two-dimensional (2-D) numerical simulation. For this purpose a simulation code is developed, solving the Poisson equation on the entire device coupled self-consistently with the drift-diffusion transport equation. We show that the charges trapped at grain boundaries in the high-permittivity (high-κ) layer induce 2-D potential fluctuations in the structure, not only in the high-κ layer, but also in the underlying oxide and semiconductor regions. These potential fluctuations are shown to significantly degrade the subthreshold behavior of the drain current. The off-state drain current and the subthreshold slope increase with respect to the case where no charge is present in the gate stack. The influence of the location of the charged grain boundaries in the stack on the subthreshold parameters is also investigated using the 2-D numerical simulation code.