1.5–2.5 nm RTP gate oxides: process feasibility, properties and limitations
Source abstract
Abstract
Abstract To support the international roadmaps' requirements, semiconductor manufacturers must develop new processing technologies, both to shrink the dimensions and to improve the performances of devices. As a consequence, gate oxidation must advance to the 1.5–2.5 nm range over the coming years, to support the sub- 0.18 μm technologies. We present here an overview of the more critical concern regarding this gate oxide downscaling. The limitations of rapid thermal processed (RTP) gate dielectric for oxide thickness
Source: openaire · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (13)
Show source-provided references
1. Buchanan · IBM J. Res. Dev. · 1999 · 43 · 24510.1147/rd.433.0245 ↗
2. Thompson · Intel Tech. J. · 1998 · Q398 · 1
3. B. Yu, H. Wang, C. Riccobene, Q. Xiang, M.-R. Lin, in: Proceedings of the Symposium of VLSI Technology, 2000, p. 90
4. Kern · RCA Rev. · 1970 · 31 · 187
5. Deal · Appl. Phys. Lett. · 1965 · 3770
6. Borisenko · 1997
7. Danel · Solid State Technol. · 1999 · S3–S6
8. DeGendt · Jpn. J. Appl. Phys. · 1998 · 37 · 464910.1143/JJAP.37.4649 ↗
9. F. Tardif, G. Qualigliotti, T. Baffert, L. Secourgeon, in: Proceedings on the Third International Symposium on Ultra Clean Processing of Silicon Surfaces, UCPSS '96, Acco, Leuven, Belgium, 1996, p. 309
10. Heyns · IBM J. Res. Dev. · 1999 · 43 · 33910.1147/rd.433.0339 ↗
11. C. Raynaud, J.-L. Autran, A. Poncet, Mater. Res. Soc. Symp. Proc. 592 (2000) in press10.1557/PROC-592-159 ↗
12. J.-L. Autran, M. Bidaud, N. Emonet, P. Masson, unpublished
13. M. Bidaud, F. Arnaud, J-L. Autran, K. Barla, ESSDERC (2000) 30410.1109/ESSDERC.2000.194775 ↗