Study of space-charge-limited currents in high-voltage TFTs based on a-Si:H

A study of space-charge-limited currents (SCLC) in high-voltage a-Si:H thin-film transistors (TFTs) is presented. For this investigation a structure with equal lengths of gated and ungated regions (L1 and L2) of 14 μm and with a width W of 350 μm was selected. Measurements were carried out in a liquid-nitrogen cryostat under high-vacuum conditions in the temperature range 100 K < T < 300 K. The gate-source voltage (VGS) and the drain-source voltage (VDS) were varied between 0 V < VGS < 15 V and 0 V < VDS < 450 V, respectively. The results show both `ohmic' and SCLC regions in relatively low-temperature I–V characteristics, but only SCLC for data taken at high temperatures. From the slope of the curves, a value of 1400 K was estimated for the characteristic temperature, Tc. The deep-trap distribution was estimated using the method of den Boer. The energy distribution Nt(E) appears as being `flat' with total trap concentrations in the range 1015 eV−1 cm−3. The relatively large value obtained for Tc indicates a trap distribution varying slowly with energy. This result is in agreement with the `flat' deep-trap distribution resulting from the analysis based on the den Boer method.