Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer

A novel polycrystalline thin-film transistor (TFT) with a very thin (<10 nm) a-Si:H buffer has been studied. The off-state leakage current of the coplanar polycrystalline silicon (poly-Si) TFT was reduced using quadruple layers of a-Si:H, SiNx, thinner a-Si:H and poly-Si and by simultaneous silicide formation of the source, drain and gate contacts. While offset-gate and lightly doped drain (LDD) poly-Si TFT structures require additional mask steps to form the field-reduced regions, the proposed poly-Si TFT needs only 2 photo-mask steps. The on–off current ratio increases from 106 to 108 by adopting a thinner a-Si:H buffer on the poly-Si.