Determination of the contribution of defect creation and charge trapping to the degradation of a-Si:H/SiN TFTs at room temperature and low voltages

In this paper is presented a qualitative investigation upon the mechanisms that cause the shift of the electrical parameters in thin film transistors (TFT). The transistors are made of amorphous hydrogenated silicon (a-Si:H) as active semiconductor layer and substoichiometric silicon nitride (SiN) as gate insulator. The work refers to the degradation at room temperature and low positive and negative gate voltage stresses. The electrical parameters: threshold voltage ($V_th$), subthreshold swing ($S$) and flat-band voltage ($V_fb$) have been determined from the dependence of the drain current on gate voltage ($I_d - V_g$) and the dependence of the capacitance on the gate voltage ($C - V_g$) measurements as function of stress time and bias.