Effect of channel length on the threshold voltage degradation of hydrogenated amorphous silicon TFTs due to the drain bias stress

Abstract The threshold voltage (VT) degradation of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) with various channel lengths of 2–100 μm has been investigated. In the presence of a drain bias, the VT degradation of a short channel a-Si:H TFT was less than that of a long channel TFT. After 30 000 s DC bias stressing, the VT shift of a short channel TFT (2 μm) was 0.35 V, while that of a long channel TFT (10 μm) was 0.6 V. The short channel effect on the VT degradation under the drain bias was negligible when the channel length exceeded 10 μm. The less VT degradation in a short channel a-Si:H TFT can be explained by the defect creation model that the VT shift is proportional to the number of carriers induced in the channel. In the presence of a drain bias, a short channel a-Si:H TFT has the smaller carrier concentration than a long channel TFT, so that a short channel a-Si:H TFT creates less defect states than a long channel TFT. The experiment with different channel widths of 100–500 μm showed no remarkable difference as observed in the case of channel length variation.