Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics
Source abstract
Abstract
Abstract An analytical model of the threshold voltage for long channel double-gate metal-oxide-semiconductor field effect transistor is developed, applicable to both symmetric and asymmetric structures with thin films ( 10). The model takes into account short-channel effects, carrier quantization and fringing-field induced barrier lowering induced by the high-permittivity gate layer. The model assumes a parabolic dependence of the potential with position in the silicon film at threshold, enabling the development of an analytical expression for the surface potential. Compared to previous models only derived for undoped films, the present approach considers both mobile charge and depleted charge terms in Poisson’s equation. The model is fully validated by numerical simulation and is used to predict the impact of the fringing-induced barrier lowering on the threshold voltage of double-gate devices as a function of the gate stack composition and the device gate length.
Source: openaire · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Silicon Carbide Semiconductor Technologies
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (18)
Show source-provided references
1. Frank · IEDM Tech. Digest · 1992 · 553
2. Wong · IEDM Tech. Digest · 1998 · 407
3. Kim · IEEE Trans. Electron. Dev. · 2001 · 48 · 29410.1109/16.902730 ↗
4. Chen · IEEE Trans. Electron. Dev. · 1996 · 43 · 138710.1109/16.535323 ↗
5. Francis · IEEE Trans. Electron. Dev. · 1994 · 41 · 71510.1109/16.285022 ↗
6. Suzuki · IEEE Trans. Electron. Dev. · 1995 · 42 · 194010.1109/16.469401 ↗
7. 2004
8. Atlas Users Manual, Silvaco, December 2002.
9. D. Munteanu, J.L. Autran, S. Harrison, T. Skotnicki, in: Proceeding of the 4th European Workshop ULIS, 2003, p. 35.
10. Mathematica User Manual, 2002.
11. Banna · IEEE Trans. Electron. Dev. · 1995 · 42 · 194910.1109/16.469402 ↗
12. Biesemans · Solid-State Electron. · 1996 · 39 · 4310.1016/0038-1101(95)00099-F ↗
13. J.L. Autran, D. Munteanu, O. Tintori, M. Aubert, E. Decarre, in: Technical proceedings of The 7th International Conference on Modeling and Simulation of Microsystems (MSM’2004), 2004, p. 171.
14. Munteanu · Solid State Electron. · 2003 · 47 · 121910.1016/S0038-1101(03)00039-X ↗
15. Ge · IEEE Trans. Electron. Dev. · 2002 · 49 · 28710.1109/16.981219 ↗
16. J.L. Autran, D. Munteanu, O. Tintori, S. Harrison, E. Decarre, T. Skotnicki, in: Technical proceedings of The 7th International Conference on Modeling and Simulation of Microsystems (MSM’2004), 2004, p. 163.
17. Harrison · IEDM Tech. Digest · 2003 · 449
18. S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, R. Pantel, D. Dutartre, Y. Morand, MP. Samson, D. Lenoble, A. Talbot, F. Boeuf, M. Sanquer, X. Jehl, J. Bustos, H. Brut, A. Cros, D. Munteanu, J-L. Autran, T. Skotnicki, High performance SON (Silicon On Nothing) Double Gate MOSFET with Perfect Electrostatic Integrity for Nanoscale Regime, VLSI Silicon Nanoelectronics Workshop, 2004.