Homo and hetero junctionless tunnel field effect transistors for mixed signal applications: a review
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Abstract
This study presents a systematic review of junctionless tunnel field effect transistor (JLTFET)–based homo- and hetero-based devices/circuits which have gained significant popularity in recent years for their performance. The divergent ranges of JLTFET-based structures are explored, and their DC/AC characteristics are discussed in detail. Basically JLTFET device exploits the advantages of both junctionless FET (JLFET) and tunnel FET (TFET) together to vanquish the major challenges that are faced by contemporary FETs. The hetero JLTFETs studied in this review uses lower band gap materials, silicon and SiXGeX-1 and high band gap material, AlGaAsat source and channel side, respectively. Also dual material gate structure in hetero JLTFET is explored for their performance improvement. Both homo and hetero structures exhibit better performance in terms of DC parameters, subthreshold slope (SS), ON-current, OFF-current and electron tunnelling rate, whereas AC parameters include unity gain cut-off frequency (ft), maximum oscillation frequency (fmax), gain bandwidth product (GBW), transconductance generation factor (TGF) and delay. The silicon-on-nothing (SON) technology–based JLTFET is studied for the performance improvement by using different dielectric materials. With respect to circuit-related study, JLTFET uses SiGeN + pocket under the gate region which act as an inverter circuit with good transient and voltage transfer characteristics (VTC). For memory circuits like SRAM, JLTFET shows better performance in terms of hold static noise margin (SNM), read SNM and write SNM.
Source: openaire · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Quantum and electron transport phenomena
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References (23)
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1. Müting J, Natzke P, Tsibizov A, Grossner U (2021) Influence of process variations on the electrical performance of SiC power MOSFETs. IEEE Transactions on Electron Devices 68(1):230–235. https://doi.org/10.1109/TED.2020.303943410.1109/TED.2020.3039434 ↗
2. Rassekh A, Sallese J-M, Jazaeri F, Fathipour M, Ionescu AM (2020) Negative capacitance double-gate junctionless FETs: a charge-based modeling investigation of swing, overdrive and short channel effect. IEEE J Electron Devices Soc 8:939–947. https://doi.org/10.1109/JEDS.2020.302097610.1109/JEDS.2020.3020976 ↗
3. Priyanka R, Chandrasekar L, Shaik RR, Pradhan KP (2021) Label free DNA detection techniques using dielectric modulated FET: inversion or tunneling? IEEE Sens J 21(2):2316–2323. https://doi.org/10.1109/JSEN.2020.301910310.1109/JSEN.2020.3019103 ↗
4. Dwivedi P, Singh R, Sengar BS, Kumar A, Garg V (2021) A new simulation approach of transient response to enhance the selectivity and sensitivity in tunneling field effect transistor-based biosensor. IEEE Sensors Journal 21(3):3201–3209. https://doi.org/10.1109/JSEN.2020.302815310.1109/JSEN.2020.3028153 ↗
5. Ahmed Z, Zhang L, Sarfraz K, Chan M (2016) Modeling CNTFET performance variation due to spatial distribution of carbon nanotubes. IEEE Trans Electron Devices 63(9):3776–4378. https://doi.org/10.1109/TED.2016.258696110.1109/TED.2016.2586961 ↗
6. ShyamSumukh S R, Moudgil A and Swaminathan S, (2015) Modelling of phosphorus and gallium doped nano-GNRFET based gas sensor.10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, Xi'an, China, pp. 347–352, https://doi.org/10.1109/NEMS.2015.7147441.10.1109/NEMS.2015.7147441 ↗
7. Ghosh B, Akram MW (2013) Junctionless tunnel field effect transistor. IEEE Electron Device Lett 34(5):584–586. https://doi.org/10.1109/LED.2013.225375210.1109/LED.2013.2253752 ↗
8. Shreya S, Khan AH, Kumar N, Amin SI, Anand S (2020) Core-shell junctionless nanotube tunnel field effect transistor: design and sensitivity analysis for biosensing application. IEEE Sens J 20(2):672–679. https://doi.org/10.1109/JSEN.2019.294488510.1109/JSEN.2019.2944885 ↗
9. Tamersit K, Djeffal F (2019) Numerical study of a new junctionless tunneling field-effect transistor based on graphene nanoribbon. IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) 2019:1–4. https://doi.org/10.1109/DTSS.2019.891509110.1109/DTSS.2019.8915091 ↗
10. Rahi, Dr & Ghosh, Bahniman& Asthana, Pranav. (2014) A simulation-based proposed high-k heterostructureAlGaAs/Si junctionless n-type tunnel FET.Journal of Semiconductors.35. https://doi.org/10.1088/1674-4926/35/11/114005.10.1088/1674-4926/35/11/114005 ↗
11. Nigam, Kaushal &Kondekar, Pravin & Sharma, Dheeraj&Raad, Bhagwan. (2016) A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism. Superlattices and Microstructures.98https://doi.org/10.1016/j.spmi.2016.07.01610.1016/j.spmi.2016.07.016 ↗
12. Rahimian Morteza, Morteza Fathipour (2017) Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric. Mater Sci Semicond Process 63:142–152. https://doi.org/10.1016/j.mssp.2016.12.01110.1016/j.mssp.2016.12.011 ↗
13. Aghandeh H, SedighZiabari SA (2017) Gate engineered heterostructurejunctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement. Superlattices Microstruct 111:103–114. https://doi.org/10.1016/j.spmi.2017.06.01810.1016/j.spmi.2017.06.018 ↗
14. Xie, H., Liu, H., Chen, S., Han, T., and Wang, S., (2020) Electrical performance of InAs/GaAs heterostructurejunctionless TFET with dual-material gate and Gaussian-doped source, Semiconductor Science Technology 35 9 https://doi.org/10.1088/1361-6641/ab9b01.10.1088/1361-6641/ab9b01 ↗
15. L. Yao, R. Liang, C. Jiang, J. Wang and J. Xu, (2014) Investigation of the junctionless line tunnel field-effect transistor. International Symposium on Next-Generation Electronics (ISNE), Kwei-Shan Tao-Yuan, Taiwan 1–2, https://doi.org/10.1109/ISNE.2014.6839326.10.1109/ISNE.2014.6839326 ↗
16. S. Singh and S. S. Chauhan, (2017) TCAD simulations of double gate junctionless tunnel field effect transistor with spacer. International Conference on Computing, Communication and Automation (ICCCA), Greater Noida, India 1441–1444, https://doi.org/10.1109/CCAA.2017.8230024.10.1109/CCAA.2017.8230024 ↗
17. Tripathi S. L, Sinha S. K, Patel G. S and Awasthi S, (2018) High performance low leakage pocket SixGe1-x junction-less single-gate tunnel FET for 10 nm technology. IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India 161–165, https://doi.org/10.1109/EDKCON.2018.8770480.10.1109/EDKCON.2018.8770480 ↗
18. Tirkey S, Sharma D, Yadav DS, Yadav S (2017) Analysis of a novel metal implant junctionless tunnel FET for better DC and analog/RF electrostatic parameters. IEEE Trans Electron Devices 64(9):3943–3950. https://doi.org/10.1109/TED.2017.273092210.1109/TED.2017.2730922 ↗
19. Kaity A, Singh S, Kondekar PN (2021) Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (SON-ED-JLTFET): a short channel effect resilient design. SILICON 13:9–23. https://doi.org/10.1007/s12633-020-00404-610.1007/s12633-020-00404-6 ↗
20. Gupta S, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET. IEEE Trans Electron Devices 64(11):4731–4737. https://doi.org/10.1109/TED.2017.275429710.1109/TED.2017.2754297 ↗
21. BhaskarAwadhiya SP, Nigam K, Kondekar PN (2017) Effect of ITC’s on linearity and distortion performance of junctionless tunnel field effect transistor, Superlattices and Microstructures, Volume 111. ISSN 293–301:0749–6036. https://doi.org/10.1016/j.spmi.2017.06.03610.1016/j.spmi.2017.06.036 ↗
22. Devi, WangkheirakpamVandana&Bhowmick, Brinda. (2018). Optimization of pocket doped junctionless TFET and its application in digital inverter. Micro & Nano Letters.14https://doi.org/10.1049/mnl.2018.508610.1049/mnl.2018.5086 ↗
23. Anju, Pandey S., Yadav S., Nigam K., Sharma D., Kondekar P.N. (2018) Realization of junctionless TFET-based power efficient 6T SRAM memory cell for Internet of Things applications. In: Somani A., Srivastava S., Mundra A., Rawat S. (eds) Proceedings of First International Conference on Smart System, Innovations and Computing. Smart Innovation, Systems and Technologies, vol 79.Springer, Singapore. https://doi.org/10.1007/978-981-10-5828-8_49.10.1007/978-981-10-5828-8_49 ↗