Thermal Expansion-Engineered Ferroelectric Transistor Arrays for Scalable Edge AI Computing

Conventional von Neumann architectures are fundamentally limited by the separation of memory and logic, leading to energy and latency bottlenecks in AI workloads. Here, we present a reconfigurable ferroelectric transistor platform based on a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure capable of switching between volatile and nonvolatile modes via gate metal engineering. By selecting tungsten (W) or titanium nitride (TiN) as gate electrodes, we modulate interfacial strain and work function to tailor ferroelectric switching in a fixed Hf 0 . 5 Zr 0 . 5 O 2 (HZO) layer. W-gated MFMIS-FeFETs exhibit a large memory window (∼11 V), >10 6 on/off ratio, 10 12 endurance cycles, and excellent uniformity across 350 devices, with 22 programmable conductance states and robust synaptic behavior. Leveraging these characteristics, a hardware-aware VGG-8 convolutional neural network simulation for CIFAR-10 classification achieved 97.2% accuracy under realistic device nonidealities. Additionally, edge detection and feature extraction were experimentally realized in FeFET arrays via analog-domain convolution using differential kernel encoding. These results validate in-memory multiply–accumulate operations, alleviating von Neumann bottlenecks while enhancing energy efficiency. This work establishes reconfigurable MFMIS-FeFET arrays as a scalable and low-power platform for neuromorphic and compute-in-memory architectures, enabling monolithic integration of memory and logic for intelligent edge systems and beyond-CMOS computing.