Dynamic-Depleted Transistor Empowering Logic-in-Coding Computing

High Resolution Image Download MS PowerPoint Slide Reconfigurable transistors are crucial for the development of high-computing-power and highly flexible logic circuits. However, conventional reconfigurable transistors, which operate in either partially depleted or fully depleted states, are limited to basic logic functions. This often requires additional circuits to switch functions, resulting in circuit redundancy and high-power consumption. Here, we propose a dynamic-depletion transistor architecture that realizes the five reconfigurable logic functions through electrostatic modulation of carrier depletion profiles. By precisely regulating the electrostatic potential of the control gate, the spatial distribution of charge carriers within the two-dimensional (2D) channel can be precisely tailored. This modulation effectively screens the electrostatic fields of other gates, thereby enabling transitions between fully depleted and partially depleted states within the same device. The dynamic switching behavior of the depletion state in the 2D WSe 2 transistor enables up to five functional integrations. Furthermore, these circuits can represent standard digital functions through inverse and additive reconfigurable logic operations, utilizing only 40 and 25% of the transistor count compared with complementary metal oxide semiconductor circuits. Building on this architecture, the designed circuit can be extended to implement a suite of reconfigurable digital image processing tasks, demonstrating a proof-of-concept for designing low-integration yet high-computing-power RLCs.