Investigation of the gate-bias induced instability for InGaZnO TFTs under dark and light illumination

Abstract Mechanism of the instability for indium–gallium–zinc oxide thin film transistors caused by gate-bias stress performed in the dark and light illumination was investigated in this paper. The parallel Vt shift with no degradation of subthreshold swing (S.S) and the fine fitting to the stretched-exponential equation indicate that charge trapping model dominates the degradation behavior under positive gate-bias stress. In addition, the significant gate-bias dependence of Vt shift demonstrates that electron trapping effect easily occurs under large gate-bias since the average effective energy barrier of electron injection decreases with increasing gate bias. Moreover, the noticeable decrease of threshold voltage (Vt) shift under illuminated positive gate-bias stress and the accelerated recovery rate in the light indicate that the charge detrapping mechanism occurs under light illumination. Finally, the apparent negative Vt shift under illuminated negative gate-bias stress was investigated in this paper. The average effectively energy barrier of electron and hole injection were extracted to clarify that the serious Vt degradation behavior comparing with positive gate-bias stress was attributed to the lower energy barrier for hole injection.