A vertical MOS-gated Esaki tunneling transistor in silicon

Abstract For the first time a vertical, MOS gated tunneling transistor in silicon is fabricated. The necessary sharp doping profile structure is created by means of MBE. Pronounced transistor action due to Esaki tunneling is demonstrated at room temperature. At a low supply voltage of −0.2 V a current gain of three magnitudes with saturation behaviour is achieved. MOS-gate, low supply voltage and exponential current increase make this device attractive for ULSI applications.