Damage-Free Smooth-Sidewall InGaAs Nanopillar Array by Metal-Assisted Chemical Etching

Producing densely packed high aspect ratio In 0.53 Ga 0.47 As nanostructures without surface damage is critical for beyond Si-CMOS nanoelectronic and optoelectronic devices. However, conventional dry etching methods are known to produce irreversible damage to III−V compound semiconductors because of the inherent high-energy ion-driven process. In this work, we demonstrate the realization of ordered, uniform, array-based In 0.53 Ga 0.47 As pillars with diameters as small as 200 nm using the damage-free metal-assisted chemical etching (MacEtch) technology combined with the post-MacEtch digital etching smoothing. The etching mechanism of In x Ga 1− x As is explored through the characterization of pillar morphology and porosity as a function of etching condition and indium composition. The etching behavior of In 0.53 Ga 0.47 As, in contrast to higher bandgap semiconductors ( e . g ., Si or GaAs), can be interpreted by a Schottky barrier height model that dictates the etching mechanism constantly in the mass transport limited regime because of the low barrier height. A broader impact of this work relates to the complete elimination of surface roughness or porosity related defects, which can be prevalent byproducts of MacEtch, by post-MacEtch digital etching. Side-by-side comparison of the midgap interface state density and flat-band capacitance hysteresis of both the unprocessed planar and MacEtched pillar In 0.53 Ga 0.47 As metal-oxide-semiconductor capacitors further confirms that the surface of the resultant pillars is as smooth and defect-free as before etching. MacEtch combined with digital etching offers a simple, room-temperature, and low-cost method for the formation of high-quality In 0.53 Ga 0.47 As nanostructures that will potentially enable large-volume production of In 0.53 Ga 0.47 As-based devices including three-dimensional transistors and high-efficiency infrared photodetectors.