Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS₂ Transistor Operating in Subthreshold Regime

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS 2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS 2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlO x /Al 2 O 3 and a double-gate structure employing high- k dielectric HfO 2 . Due to the superior subthreshold characteristics, monolayer WS 2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS 2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage ( V DD ) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm –1 at V DD = 1 V. In addition, the monolayer WS 2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS 2 for high-gain and low-power logic circuits and validate the practical application in large areas.