Unified Steep‐Slope Switching and Non‐Volatile Memory in a Complementarily Stabilized van der Waals Ferroelectric Transistor

ABSTRACT Achieving both steep‐slope switching and robust non‐volatile memory within a single transistor would enable new device concepts for low‐power and logic‐in‐memory architectures. Conventional negative‐capacitance FETs (NC‐FETs) are designed to suppress ferroelectric bistability to enable hysteresis‐free sub‐thermionic switching, whereas ferroelectric FETs (Fe‐FETs) exploit bistable polarization to provide non‐volatile memory, leaving the two operating regimes largely separate in practice. Here, we report a van der Waals ferroelectric negative‐capacitance transistor (FeNC‐FET) that simultaneously realizes stabilized negative capacitance and intrinsic bistable polarization by employing a CIPS/h‐BN/α‐In ₂ Se ₃ trilayer gate stack. Landau–Khalatnikov analysis and polarization–voltage measurements confirm complementary ferroelectric roles in which CIPS provides static negative curvature, h‐BN enables charge compensation, and α‐In ₂ Se ₃ supplies non‐volatile polarization. This cooperative mechanism enables steep sub‐threshold swings of 35 mV/dec (forward) and 51 mV/dec (reverse), a ∼3 V memory window, long retention (>10 ⁴ s), and endurance exceeding 2500 cycles. The device further performs AND, OR, and majority logic‐in‐memory operations using 10 µs pulses with clear ON/OFF separation. These results establish the FeNC‐FET as a compact platform that combines steep‐slope switching with non‐volatile programmability in a single device, enabling low‐bias readout, short‐pulse programming, and robust logic‐in‐memory operation.