Virtualization as a New Scaling Law for Semiconductor Devices Beyond Geometric Scaling

ABSTRACT As Moore's‐law–driven geometric scaling nears physical, economic, and sustainability limits, semiconductor progress is increasingly constrained by the cost and latency of physical iteration. This Perspective argues that AI enables virtualization as a complementary scaling law: progress scales with how much trustworthy virtual evidence can replace exhaustive fabrication, testing, and qualification across the device lifecycle. We show how virtualization emerges in i) design and modeling via surrogate and physics‐informed learning, inverse design, and uncertainty‐aware exploration; ii) fabrication and packaging via digital twins, virtual metrology, and reinforcement learning; and iii) qualification via defect inference and reliability modeling that provide earlier risk signals. We outline boundary conditions—trust and uncertainty, cross‐stage coherence, sustainability, and governance—and argue that future innovation will depend not only on geometric shrinkage, but also on the fidelity, integration, and stewardship of virtual evidence.