CMOS‐Compatible Pressure‐Assisted Solid‐Phase‐Diffusion Technique for Large‐Area Multilayer Graphene Synthesis

Abstract Multilayer graphene (MLG) interconnects, enabled by subtractive etching and intercalation doping, have emerged as a promising solution for advanced Complementary Metal‐Oxide‐Semiconductor (CMOS) technology nodes, where conventional metal interconnects face escalating challenges, including increased resistance, self‐heating, electromigration, and integration complexity. However, traditional MLG synthesis methods typically require high temperatures (>600 °C) and involve transfer from metal catalysts to dielectric substrates—practices incompatible with CMOS back‐end‐of‐line (BEOL) thermal budgets (<500 °C) and prone to introducing defects and wrinkles that hinder wafer‐scale integration. To overcome these limitations, this group pioneered a CMOS‐compatible, transfer‐free growth technique based on pressure‐assisted solid‐phase diffusion, which enables direct synthesis of high‐quality MLG within BEOL constraints. Combined with optimized intercalation doping ‐ originally introduced by this group ‐ this approach achieves significantly enhanced electrical conductivity, exceeding that of sub‐30 nm metal wires, with excellent electromigration reliability. This breakthrough has garnered broad attention for its potential to transform interconnect technology and accelerate the integration of graphene into mainstream semiconductor manufacturing. This article presents the scientific rationale, materials physics, and process innovations underpinning this scalable technology, highlighting how catalyst selection, carbon sources, and process parameters govern MLG quality and performance. Beyond interconnects, this work lays a foundation for deploying graphene in optoelectronics, spintronics, photovoltaics, and flexible electronics.