Selectively Self‐Aligned Sol‐Gel Copper Oxide for Large‐Area Multi‐Valued Logic Devices (Small 26/2025)
Source abstract
Abstract
Heterojunction Transistors In article number 2407497, Jun-Gyu Choi, Sungjun Park, and co-workers illustrate a wafer-scale array of solution-processed heterojunction transistors fabricated via SAM-assisted selective patterning. This novel strategy highlights a promising alternative to conventional photolithography by effectively addressing the challenges posed by partially overlapped junction structures. A magnified junction interface showcases efficient carrier transport, enabled by the partially overlapped architecture of the metal oxide heterojunction.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Semiconductor materials and devices · Extraction and Separation Processes · Nanomaterials for catalytic reactions
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Affiliations
Department of Intelligence Semiconductor and Engineering Ajou University Suwon Republic of Korea
Department of Electrical and Computer Engineering Ajou University Suwon 16499 Republic of Korea
Department of Chemistry Purdue University West Lafayette Indiana 47907 USA
References
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