Microstructure Control Over Low−Indium Oxide Semiconductors to Obtain Synchronous Optimization of Their TFT Mobility and Stability

ABSTRACT Balancing device performance and stability remains a persistent challenge in amorphous oxide semiconductor thin−film transistors (AOS TFTs), which are increasingly important for advanced displays. Conventional strategies—such as incorporating new materials with low electron effective mass or engineering crystallinity—face limitations including scarce candidates and high thermal budgets, constraining the progress of AOS TFTs. Here, an Al−induced microstructure control (AIMC) method to lower the energy barrier for phase transitions and regulate microstructural ordering at relatively low processing temperatures is introduced. By combining AIMC with chemical etching, a microstructure regulation (MR) layer in low−indium (∼24 at.%) InSnZnO (ITZO) films, achieving a dense, defect−suppressing, grain boundary−free structure is constructed. TFTs with this layer exhibits markedly enhanced field−effect mobility ( µ _FE = 67.4 cm ² /V·s) and improved NBIS stability (Δ V _TH ≈ −2.53 V). To further strengthen NBIS stability, bilayer stacked−channel TFTs are developed, integrating the MR layer with ITZO:Pr as carrier transport and photoelectron relaxation layers, respectively. The synergistic design yields well−balanced performance and reliability, offering a promising route for next generation high−end display backplanes.