Scalable Inter‐Dielectric Engineering via Vapor‐Phase Synthesis Process for Top‐Gate MoS ₂ Thin‐Film Transistor

Abstract 2D semiconductors are promising channel materials for next‐generation thin‐film transistors (TFTs) in Internet of Things (IoT) devices. However, their inert, dangling‐bond‐free surfaces make uniform high‐ k dielectric integration challenging and can lead to interface defect formation. Here, a scalable inter‐dielectric engineering strategy is introduced to address this challenge, using initiated chemical vapor deposition (iCVD) to deposit an ultrathin nonpolar poly(1,3,5‐trimethyl‐1,3,5‐trivinylcyclotrisiloxane) (pV3D3) film as an interlayer between MoS ₂ and HfO ₂ . This pV3D3 buffer layer forms uniformly without pinholes or clusters on MoS ₂ , yielding excellent interface quality and effectively suppressing HfO ₂ ‐induced uncontrollable doping effect and trap formation in MoS ₂ . As a result, the MoS ₂ top‐gate transistors with pV3D3/HfO ₂ dielectric exhibit nearly ideal switching characteristics, including a subthreshold swing ( SS ) of 60.9 mV dec ⁻¹ , negligible hysteresis of ≈20 mV, and low interface trap density ( D _it,avg ) of 8.9 × 10 ¹⁰ cm ⁻² e ⁻¹ V ⁻¹ . Furthermore, an overlapping top‐gate structure design minimizes contact resistance, achieving an I _ON / I _OFF ratio above 10 ⁸ , a field‐effect mobility (µ _FE ) of 19.2 cm ² V ⁻¹ s ⁻¹ , and minimum subthreshold swing ( SS _min ) of 80.6 mV dec ⁻¹ . This iCVD based inter‐dielectric method is further validated on a flexible MoS ₂ top‐gate transistors and logic circuits, demonstrating its potential for scalable and large‐area high‐performance 2D electronics.