Mobility‐Enhancement Effect in Ultrashort‐Gate Field‐Effect Transistors

Mobility enhancement is a mechanical stress response of semiconductors employed in high‐performance transistors. This study investigates the mobility‐enhancement effect on nanoscale gate‐length transistors with silicon‐germanium material. An electrical–thermal–mechanical self‐consistent analysis is employed to predict the effect of mechanical stress on the performances of transistors. A direct current analysis reveals that mechanical stress weakens performances under certain conditions, including <100> n‐channel field‐effect transistors (NFETs) under compressive stress and <110> p‐channel field‐effect transistors under tensile stress. The results indicate that device performance cannot be improved using mobility enhancement. Negative mobility enhancement presents an issue when the quasi‐Fermi potential gradient weakens before its potential reaches the electrode. The πσ product must be smaller than a certain value to avoid this problem, and its criteria are independent of the structural design of the source–drain distance and electrical parameters of the drain–source bias voltage. The NFET stress limitation is severe when a larger value is considered. When adopting silicon material, its maximum stress must be limited to the sub‐GPa range.