Show source-provided references
2. Timp, G.; Bourdelle, K. K.; Bower, J. E.; Baumann, F. H.; Boone, T.; Cirelli, R.; Evans-Lutterodt, K.; Garno, J.; Ghetti, A.; Gossmann, H.; Green, M.; Jacobson, D.; Kim, Y.; Kleiman, R.; Klemens, F.; Kornlit, A.; Lochstampfor, C.; Mansfield, W.; Moccio, S.; Muller, D. A.; Ocola, I. E.; O’Malley, M. I.; Rosamilia, J.; Sapjeta, J.; Silverman, P.; Sorsch, T.; Tennant, D. M.; Timp, W.; Weir, B. E.In Progress Toward 10 nm CMOS Devices, International Electron Devices Meeting, 1998; pp 615–618.
4. Mertens, H.; Ritzenthaler, R.; Hikavyy, A.; Kim, M. S.; Tao, Z.; Wostyn, K.; Chew, S. A.; De Keersgieter, A.; Mannaert, G.; Rosseel, E.; Schram, T.; Devriendt, K.; Tsvetanova, D.; Dekkers, H.; Demuynck, S.; Chasin, A.; Van Besien, E.; Dangol, A.; Godny, S.; Douhard, B.; Bosman, N.; Richard, O.; Geypen, J.; Bender, H.; Barla, K.; Mocuta, D.; Horiguchi, N.; Thean, A. V. Y.In Gate-All-Around MOSFETs Based On Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates, IEEE Symposium on VLSI Technology, 2016; pp 1–2.
10.1109/VLSIT.2016.7573416 ↗5. Kim, S. D.; Guillorn, M.; Lauer, I.; Oldiges, P.; Hook, T.; Na, M. H.In Performance Trade-Offs in FinFET and Gate-All-Around Device Architectures for 7nm-Node and Beyond, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015; pp 1–3.
10.1109/S3S.2015.7333521 ↗6. Suk, S. D.; Lee, S. Y.; Kim, S. M.; Yoon, E. J.; Kim, M. S.; Li, M.; Oh, C. W.; Yeo, K. H.; Kim, S. H.; Shin, D. S.; Lee, K. H.; Park, H. S.; Han, J. N.; Park, C. J.; Park, J. B.; Kim, D. W.; Park, D.; Ryu, B. I.In High Performance 5nm Radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication on Bulk Si Wafer, Characteristics, and Reliability, IEDM Technical Digest, 2005; pp 717–720.
7. Bangsaruntip, S.; Balakrishnan, K.; Cheng, S. L.; Chang, J.; Brink, M.; Lauer, I.; Bruce, R. L.; Engelmann, S. U.; Pyzyna, A.; Cohen, G. M.; Gignac, L. M.; Breslin, C. M.; Newbury, J. S.; Klaus, D. P.; Majumdar, A.; Sleight, J. W.; Guillorn, M. A.In Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10 nm Node and Beyond, IEEE International Electron Devices Meeting, 2013; pp 20.2.1–20.2.4.
10.1109/IEDM.2013.6724667 ↗8. Hur, S. G.; Yang, J. G.; Kim, S. S.; Lee, D. K.; An, T.; Nam, K. J.; Kim, S. J.; Wu, Z.; Lee, W.; Kwon, U.; Lee, K. H.; Park, Y.; Yang, W.; Choi, J.; Kang, H. K.; Jung, E. S.In A Practical Si Nanowire Technology with Nanowire-On-Insulator Structure for Beyond 10nm Logic Technologies, IEEE International Electron Devices Meeting, 2013; pp 26.5.1–26.5.4.
10.1109/IEDM.2013.6724698 ↗14. Roman B. · J. Phys.: Condens. Matter · 2010 · 22 · 493101
32. Borisov, V.; Scheible, J. InLithography Hotspots Detection Using Deep Learning, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2018; pp 145–148.
10.1109/SMACD.2018.8434561 ↗34. Solecky, E.; Patterson, O. D.; Stamper, A.; McLellan, E.; Buengener, R.; Vaid, A.; Hartig, C.; Bunday, B.; Arceo, A.; Cepler, A. InIn-Line E-Beam Wafer Metrology and Defect Inspection: the End of an Era for Image-Based Critical Dimensional Metrology? New Life for Defect Inspection, Metrology, Inspection, and Process Control for Microlithography XXVII, 2013; pp 8681.0D.1–8681.0D.19.
10.1117/12.2010007 ↗35. Solecky, E.; Rasafar, A.; Cantone, J.; Bunday, B.; Vaid, A.; Patterson, O.; Stamper, A.; Wu, K.; Buengener, R.; Weng, W.; Dai, X. InIn-Line E-Beam Metrology and Defect Inspection: Industry Reflections, Hybrid E-Beam Opportunities, Recommendations and Predictions, Metrology, Inspection, and Process Control for Microlithography XXXI, 2017; pp 10145.0R.1–10145.0R.18.
10.1117/12.2261524 ↗36. Lorusso, G. F.; Ohashi, T.; Yamaguchi, A.; Inoue, O.; Sutani, T.; Horiguchi, N.; Bömmels, J.; Wilson, C. J.; Briggs, B.; Tan, C. L.; Raymaekers, T.; Delhougne, R.; Bosch, G. V. d.; Piazza, L. D.; Kar, G. S.; Furnémont, A.; Fantini, A.; Donadio, G. L.; Souriau, L.; Crotti, D.; Yasin, F.; Appeltans, R.; Rao, S.; Simone, D. D.; Delgadillo, P. R.; Leray, P.; Charley, A.L.; Zhou, D.; Veloso, A.; Collaert, N.; Hasumi, K.; Koshihara, S.; Ikota, M.; Okagawa, Y.; Ishimoto, T.In Enabling CD SEM Metrology for 5nm Technology Node and Beyond, Metrology, Inspection, and Process Control for Microlithography XXXI, 2017; pp 10145.12.1–10145.12.9.
10.1117/12.2257468 ↗37. Jan, T.In Neural Network Based Threat Assessment for Automated Visual Surveillance, IEEE International Joint Conference on Neural Networks, 2004; pp 1309–1312.
10.1109/IJCNN.2004.1380133 ↗43. Nair, V.; Hinton, G. E.In Rectified Linear Units Improve Restricted Boltzmann Machines; International Conference on Machine Learning; Omnipress: 2010; pp 807–814.
44. Xu, B.; Wang, N.; Chen, T.; Li, M. Empirical Evaluation of Rectified Activations in Convolutional Network.arXiv:1505.00853 [cs, stat]2015.
45. Scherer, D.; Müller, A.; Behnke, S.In Evaluation of Pooling Operations in Convolutional Architectures for Object Recognition, International Conference on Artificial Neural Networks; Springer, 2010; pp 92–101.
10.1007/978-3-642-15825-4_10 ↗46. Lee, C. Y.; Gallagher, P. W.; Tu, Z. Generalizing Pooling Functions in Convolutional Neural Networks: Mixed, Gated, and Tree.arXiv:1509.08985 [cs, stat]2015.
47. Chollet, F. Keras. https://github.com/fchollet/keras.
48. Nwankpa, C.; Ijomah, W.; Gachagan, A.; Marshall, S. Activation Functions: Comparison of Trends in Practice and Research for Deep Learning.arXiv:1811.03378 [cs]2018.
49. Heaton J. · 2013 · 1
50. Ruder, S. An Overview of Gradient Descent Optimization Algorithms.arXiv:1609.04747 [cs]2017.
52. Simonyan, K.; Zisserman, A. Very Deep Convolutional Networks for Large-Scale Image Recognition.arXiv:1409.1556 [cs]2015.
53. Das, S.; Hung, J.; Halder, S.; Schelcher, G.; Koret, R.; Turovets, I.; Saib, M.; Charley, A.L.; Sandelbach, M.; Ger, A.; Leray, P.In Machine Learning for Predictive Electrical Performance Using OCD; Metrology, Inspection, and Process Control for Microlithography XXXIII, 2019; pp 10959.0F.1–10959.0F.9.
10.1117/12.2515806 ↗