Elemental devices, circuits and processes for a monolithic Si/III–V–N alloy OEIC

Abstract The fabrication process of elemental devices for novel OEICs were studied based on a Si/III–V–N alloy/Si structure. The elemental devices are MOS transistors and LEDs fabricated on a Si capping layer and III–V–N alloy layer, respectively. The fabrication process was simplified by combining the gate oxidation with the post-annealing of ion implantation and thermal annealing for increasing the light-emission efficiency of GaPN alloys. Surface inversion was observed in a MOS diode fabricated on a Si/GaPN/Si structure. A GaPN/GaP DH LED grown on a GaP substrate was fabricated as well. It was clarified that the elemental devices could be principally fabricated by a simplified fabrication process although several problems have to be overcome. Key issues are the reduction of N-related point defects, the doping control for the III–V–N alloy and Si layers and the reduction of the surface roughness of the Si capping layer.