journal article·2026-02-09Open access

Mapping diverse hysteresis dynamics in scaled MoS2 FETs using the universal method derived from TCAD modeling

Y. Z. Lv, Y. H. Wu, H. H. Cai, Yu.Yu. Illarionov

npj 2D Materials and Applications· Volume 10· Issue 1

Abstract

Abstract Field-effect transistors (FETs) with 2D channels have already approached trial FAB integration. However, reliability limitations caused by various defects impede their smooth way forward. Still the ongoing research is mostly focused on pure technology aspects, while reliability is often recalled only to manifest a “negligible” hysteresis for a randomly measured gate transfer curve. In fact the hysteresis dynamics contain unique fingerprints of various mechanisms which may coexist or cancel each other, especially in scaled FETs where defects can simultaneously interact with multiple interfaces. To fill this gap, here by doing TCAD modeling for nanoscale MoS 2 /HfO 2 FETs we first introduce the universal hysteresis mapping method which can correctly capture diverse hysteresis dynamics such as conventional clockwise (CW) and counterclockwise (CCW) hysteresis, CW/CCW switching and time separation. Then we validate this method using experimental data for MoS 2 FETs and demonstrate that it can be used directly for any measured hysteresis dataset to reveal additional physical insights with no need for TCAD modeling.
Source: crossref · Quality: baseline

Research context

OpenAlex topics: Ferroelectric and Negative Capacitance Devices · Advancements in Semiconductor Devices and Circuit Design · Advanced Memory and Neural Computing

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

References (42)

Show source-provided references
1. Wachter, S., Polyushkin, D. K., Bethge, O. & Mueller, T. A microprocessor based on a two-dimensional semiconductor. Nat. Commun. 8, 14948 (2017).10.1038/ncomms14948 ↗
2. Lemme, M., Akinwande, D., Huyghebaert, C. & Stampfer, C. 2D materials for future heterogeneous electronics. Nat. Commun. 13, 1392 (2022).10.1038/s41467-022-29001-4 ↗
3. Huang, J.-K. et al. High-κ perovskite membranes as insulators for two-dimensional transistors. Nature 605, 262–267 (2022).10.1038/s41586-022-04588-2 ↗
4. Tan, C. et al. 2D Fin field-effect transistors integrated with epitaxial high-k gate oxide. Nature 616, 66–72 (2023).10.1038/s41586-023-05797-z ↗
5. Pendurthi, R. et al. Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors. Nat. Nanotechnol. 19, 970–977 (2024).10.1038/s41565-024-01705-2 ↗
6. Asselberghs, I. et al. Wafer-scale integration of double gated WS2 transistors in 300mm Si CMOS Fab. In IEEE International Electron Devices Meeting (IEDM) 40–2 (IEEE, 2020).10.1109/IEDM13553.2020.9371926 ↗
7. Dorow, C. et al. Gate length scaling beyond Si: mono-layer 2D channel FETs robust to short channel effects. In IEEE International Electron Devices Meeting (IEDM) 7–5 (IEEE, 2022).10.1109/IEDM45625.2022.10019524 ↗
8. Chung, Y.-Y. et al. Stacked channel transistors with 2D materials: an integration perspective. In IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2024).
9. Mortelmans, W. et al. Gate oxide module development for scaled GAA 2D FETs enabling SS< 75mV/d and record Idmax> 900μA/μm at Lg< 50nm. In IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2024).10.1109/IEDM50854.2024.10873417 ↗
10. Schwierz, F., Pezoldt, J. & Granzner, R. Two-dimensional materials and their prospects in transistor electronics. Nanoscale 7, 8261–8283 (2015).10.1039/C5NR01052G ↗
11. Das, S. et al. Transistors based on two-dimensional materials for future integrated circuits. Nat. Electron. 4, 786–799 (2021).10.1038/s41928-021-00670-1 ↗
12. Illarionov, Y. et al. Insulators for 2D nanoelectronics: the gap to bridge. Nat. Commun. 11, 3385 (2020).10.1038/s41467-020-16640-8 ↗
13. Jayachandran, D. et al. Three-dimensional integration of two-dimensional field-effect transistors. Nature 625, 276–281 (2024).10.1038/s41586-023-06860-5 ↗
14. Illarionov, Y. et al. Variability and high temperature reliability of graphene field-effect transistors with thin epitaxial CaF2 insulators. npj 2D Mater. Appl. 8, 23 (2024).10.1038/s41699-024-00461-0 ↗
15. Kaczer, B., Roussel, P., Grasser, T. & Groeseneken, G. Statistics of multiple trapped charges in the gate oxide of deeply scaled MOSFET devices-application to NBTI. IEEE Electron Dev. Lett. 31, 411–413 (2010).10.1109/LED.2010.2044014 ↗
16. Grasser, T. Stochastic charge trapping in oxides: from random telegraph noise to bias temperature instabilities. Microelectron. Reliab. 52, 39–70 (2012).10.1016/j.microrel.2011.09.002 ↗
17. Markov, S., Amoroso, S., Gerrer, L., Adamu-Lema, F. & Asenov, A. Statistical interactions of multiple oxide traps under BTI stress of nanoscale MOSFETs. IEEE Electron Dev. Lett. 34, 686–688 (2013).10.1109/LED.2013.2253541 ↗
18. Badaroglu, M. More Moore. In IEEE International Roadmap for Devices and Systems Outbriefs, 01–38 https://doi.org/10.1109/IRDS54852.2021.00010 (Santa Clara, CA, USA 2021).10.1109/IRDS54852.2021.00010 ↗
19. Roh, J., Lee, J.-H., Jin, S. H. & Lee, C. Negligible hysteresis of molybdenum disulfide field-effect transistors through thermal annealing. J. Inf. Disp. 17, 103–108 (2016).10.1080/15980316.2016.1179688 ↗
20. Vu, Q. et al. Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS2 field-effect transistors. 2D Mater. 5, 031001 (2018).10.1088/2053-1583/aab672 ↗
21. Cho, H. W. et al. Direct growth of orthorhombic Hf0.5Zr0.5O2 thin films for hysteresis-free MoS2 negative capacitance field-effect transistors. npj 2D Mater. Appl. 5, 46 (2021).10.1038/s41699-021-00229-w ↗
22. Venkatakrishnarao, D. et al. Liquid metal oxide-assisted integration of high-k dielectrics and metal contacts for two-dimensional electronics. ACS Nano 18, 26911–26919 (2024).10.1021/acsnano.4c08554 ↗
23. Fan, X. et al. 2D edge-seeded heteroepitaxy of ultrathin high-κ dielectric CaNb2O6 for 2D field-effect transistors. Nat. Commun. 16, 2585 (2025).10.1038/s41467-025-57773-y ↗
24. Lan, H.-Y. et al. Reliability of high-performance monolayer MoS2 transistors on scaled high-κ HfO2. npj 2D Mater. Appl. 9, 5 (2025).10.1038/s41699-025-00527-7 ↗
25. Provias, A. et al. Reliability assessment of double-gated wafer-scale MoS2 field effect transistors through hysteresis and bias temperature instability analyses. In IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023).10.1109/IEDM45741.2023.10413755 ↗
26. Grasser, T. et al. The paradigm shift in understanding the bias temperature instability: from reaction-diffusion to switching oxide traps. IEEE Trans. Electron Devices 58, 3652–3666 (2011).10.1109/TED.2011.2164543 ↗
27. GTS Minimos-NT User Manual. Global TCAD Solutions, Vienna, Austria, (2022).
28. Alkauskas, A., Yan, Q. & Van de Walle, C. G. First-principles theory of nonradiative carrier capture via multiphonon emission. Phys. Rev. B 90, 075202 (2014).10.1103/PhysRevB.90.075202 ↗
29. Illarionov, Y. et al. Long-term stability and reliability of black phosphorus field-effect transistors. ACS Nano 10, 9543–9549 (2016).10.1021/acsnano.6b04814 ↗
30. Illarionov, Y. et al. Energetic mapping of oxide traps in MoS2 field-effect transistors. 2D Mater. 4, 025108 (2017).10.1088/2053-1583/aa734a ↗
31. Knobloch, T. et al. A physical model for the hysteresis in MoS2 transistors. IEEE J. Electron Dev. Soc. 6, 972–978 (2018).10.1109/JEDS.2018.2829933 ↗
32. Knobloch, T. et al. Modeling the Performance and Reliability of Two-Dimensional Semiconductor Transistors. In IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023).10.1109/IEDM45741.2023.10413824 ↗
33. Ngo, T. et al. The critical role of 2D TMD interfacial layers for pFET performance. In IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2024).10.1109/IEDM50854.2024.10873377 ↗
34. Rasmussen, F. & Thygesen, K. Computational 2D materials database: electronic structure of transition-metal dichalcogenides and oxides. J. Phys. Chem. C. 119, 13169–13183 (2015).10.1021/acs.jpcc.5b02950 ↗
35. Rzepa, G. et al. Comphy—a compact-physics framework for unified modeling of BTI. Microel. Reliab. 85, 49–65 (2018).10.1016/j.microrel.2018.04.002 ↗
36. Waldhoer, D. et al. Toward automated defect extraction from bias temperature instability measurements. IEEE Trans. Electron Devices 68, 4057–4063 (2021).10.1109/TED.2021.3091966 ↗
37. Waldhoer, D. et al. Comphy v3.0—a compact-physics framework for modeling charge trapping related reliability phenomena in MOS devices. Microelectron. Reliab. 146, 115004 (2023).10.1016/j.microrel.2023.115004 ↗
38. Ryou, J., Kim, Y.-S., Kc, S. & Cho, K. Monolayer MoS2 bandgap modulation by dielectric environments and tunable bandgap transistors. Sci. Rep. 6, 29184 (2016).10.1038/srep29184 ↗
39. Illarionov, Y. et al. The role of charge trapping in MoS2/SiO2 and MoS2/hBN field-effect transistors. 2D Mater. 3, 035004 (2016).10.1088/2053-1583/3/3/035004 ↗
40. Rahman, M. S. et al. Accurate bias stress instability measurements in high-performance ITO FETs using modified on-the-fly technique. IEEE Electron Dev. Lett. 46, 864–867 (2025).10.1109/LED.2025.3554214 ↗
41. Wahid, S. et al. Role of oxygen deficiencies on the stability of indium tin oxide (ITO) transistors. IEEE Electron Dev. Lett. 46, 1–4 (2025).10.1109/LED.2025.3587706 ↗
42. Illarionov, Y. et al. Improved hysteresis and reliability of MoS2 transistors with high-quality CVD growth and Al2O3 encapsulation. IEEE Electron Dev. Lett. 38, 1763–1766 (2017).10.1109/LED.2017.2768602 ↗