Low-power 2D gate-all-around logics via epitaxial monolithic 3D integration
Source abstract
Abstract
Innovations in device architectures and materials promote transistor miniaturization for improved performance, energy efficiency and integration density. At foreseeable ångström nodes, a gate-all-around (GAA) field-effect transistor based on two-dimensional (2D) semiconductors would provide excellent electrostatic gate controllability to achieve ultimate power scaling and performance delivering. However, a major roadblock lies in the scalable integration of 2D GAA heterostructures with atomically smooth and conformal interfaces. Here we report a wafer-scale multi-layer-stacked single-crystalline 2D GAA configuration achieved with low-temperature monolithic three-dimensional integration, in which high-mobility 2D semiconductor Bi2O2Se was epitaxially integrated by high-κ layered native-oxide dielectric Bi2SeO5 with an atomically smooth interface, enabling a high electron mobility of 280 cm2 V-1 s-1 and a near-ideal subthreshold swing of 62 mV dec-1. The scaled 2D GAA field-effect transistor with 30 nm gate length exhibits an ultralow operation voltage of 0.5 V, a high on-state current exceeding 1 mA μm-1, an ultralow intrinsic delay of 1.9 ps and an energy-delay product of 1.84 × 10-27 Js μm-1. This work demonstrates a wafer-scale 2D-material-based GAA system with valid performance and power merits, holding promising prospects for beyond-silicon monolithic three-dimensional circuits.
Source: europepmc · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Semiconductor materials and devices · Advanced Memory and Neural Computing · Advancements in Semiconductor Devices and Circuit Design
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (54)
Show source-provided references
1. Waldrop, M. The chips are down for Moore’s law. Nature 530, 144 (2016).10.1038/530144a ↗
2. Lundstrom, M. Moore’s law forever? Science 299, 210–211 (2003).10.1126/science.1079567 ↗
3. Bae, G. et al. 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications. In 2018 IEEE International Electron Devices Meeting (IEDM) 28.27.21–28.27.24 (IEEE, 2018).10.1109/IEDM.2018.8614629 ↗
4. Huang, C. Y. et al. 3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling. In 2020 IEEE International Electron Devices Meeting (IEDM) 20.26.21–20.26.24 (IEEE, 2020).10.1109/IEDM13553.2020.9372066 ↗
5. Ritzenthaler, R. et al. Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced vertical nanowires separation, new work function metal gate solutions, and DC/AC performance optimization. In 2018 IEEE International Electron Devices Meeting (IEDM) 21.25.21–21.25.24 (IEEE, 2018).10.1109/IEDM.2018.8614528 ↗
6. Loubet, N. et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In 2017 Symposium on VLSI Technology (VLSIT) T230–T231 (IEEE, 2017).
7. Theis, T. N. & Wong, H. S. P. The end of Moore’s law: a new beginning for information technology. Comput. Sci. Eng. 19, 41–50 (2017).10.1109/MCSE.2017.29 ↗
8. Liu, C. et al. Two-dimensional materials for next-generation computing technologies. Nat. Nanotechnol. 15, 545–557 (2020).10.1038/s41565-020-0724-3 ↗
9. Jiang, J., Xu, L., Qiu, C. & Peng, L. M. Ballistic two-dimensional InSe transistors. Nature 616, 470–475 (2023).10.1038/s41586-023-05819-w ↗
10. Wu, F. et al. Vertical MoS2 transistors with sub-1-nm gate lengths. Nature 603, 259–264 (2022).10.1038/s41586-021-04323-3 ↗
11. Shen, P. C. et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593, 211–217 (2021).10.1038/s41586-021-03472-9 ↗
12. Lu, D. et al. Monolithic three-dimensional tier-by-tier integration via van der Waals lamination. Nature 630, 340–345 (2024).10.1038/s41586-024-07406-z ↗
13. Tan, C. et al. 2D fin field-effect transistors integrated with epitaxial high-κ gate oxide. Nature 616, 66–72 (2023).10.1038/s41586-023-05797-z ↗
14. Wu, J. et al. High electron mobility and quantum oscillations in non-encapsulated ultrathin semiconducting Bi2O2Se. Nat. Nanotech. 12, 530–534 (2017).10.1038/nnano.2017.43 ↗
15. Cao, W. et al. The future transistors. Nature 620, 501–515 (2023).10.1038/s41586-023-06145-x ↗
16. Illarionov, Y. Y. et al. Insulators for 2D nanoelectronics: the gap to bridge. Nat. Commun. 11, 3385 (2020).10.1038/s41467-020-16640-8 ↗
17. Chung, Y. Y. et al. First demonstration of GAA monolayer-MoS2 nanosheet nFET with 410 μA/μm ID 1V VD at 40nm gate length. In 2022 International Electron Devices Meeting (IEDM) 34.35.31–34.35.34 (IEEE, 2022).10.1109/IEDM45625.2022.10019563 ↗
18. Xiong, X. et al. Demonstration of vertically-stacked CVD monolayer channels: MoS2 nanosheets GAA-FET with Ion > 700 µA/µm and MoS2/WSe2 CFET. In 2021 IEEE International Electron Devices Meeting (IEDM) 7.5.1–7.5.4 (IEEE, 2021).10.1109/IEDM19574.2021.9720533 ↗
19. Huang, X. et al. Ultrathin multibridge channel transistor enabled by van der Waals assembly. Adv. Mater. 33, e2102201 (2021).
20. Xu, Y. et al. Scalable integration of hybrid high-κ dielectric materials on two-dimensional semiconductors. Nat. Mater. 22, 1078–1084 (2023).10.1038/s41563-023-01626-w ↗
21. Chen, Z. Gate-all-around nanosheet transistors go 2D. Nat. Electron. 5, 830–831 (2022).10.1038/s41928-022-00899-4 ↗
22. Zhang, Y. et al. A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5 nm. Nat. Electron. 5, 643–649 (2022).10.1038/s41928-022-00824-9 ↗
23. Li, T. et al. A native oxide high-κ gate dielectric for two-dimensional electronics. Nat. Electron. 3, 473–478 (2020).10.1038/s41928-020-0444-6 ↗
24. Davoudi, M. R. et al. Multi-scale modeling of transistors based on the 2D semiconductor Bi2O2Se. In 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 49–52 (IEEE, 2023).10.23919/SISPAD57422.2023.10319609 ↗
25. Knobloch, T. et al. Modeling the performance and reliability of two-dimensional semiconductor transistors. In 2023 International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023).10.1109/IEDM45741.2023.10413824 ↗
26. Sung-Young, L. et al. A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics. IEEE Trans. Nanotechnol. 2, 253–257 (2003).10.1109/TNANO.2003.820777 ↗
27. International Roadmap for Devices and Systems 2023 Edition (IRDS, 2024); https://irds.ieee.org/
28. Auth, C. et al. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. In 2017 IEEE International Electron Devices Meeting 29.21.21–29.21.24 (IEEE, 2017).10.1109/IEDM.2017.8268472 ↗
29. Natarajan, S. et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size. In 2014 IEEE International Electron Devices Meeting (IEDM) 3.7.1–3.7.3 (IEEE, 2014).10.1109/IEDM.2014.7046976 ↗
30. Auth, C. et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In 2012 Symposium on VLSI Technology (VLSIT) 131–132 (IEEE, 2012).10.1109/VLSIT.2012.6242496 ↗
31. Fan, D. et al. Two-dimensional semiconductor integrated circuits operating at gigahertz frequencies. Nat. Electron. 6, 879–887 (2023).10.1038/s41928-023-01052-5 ↗
32. Kresse, G. & Furthmuller, J. Efficiency of ab-initio total energy calculations for metals and semiconductors using a plane-wave basis set. Comp. Mater. Sci. 6, 15–50 (1996).10.1016/0927-0256(96)00008-0 ↗
33. Kresse, G. & Furthmuller, J. Efficient iterative schemes for ab initio total-energy calculations using a plane-wave basis set. Phys. Rev. B 54, 11169–11186 (1996).10.1103/PhysRevB.54.11169 ↗
34. Das, S. et al. Transistors based on two-dimensional materials for future integrated circuits. Nat. Electron. 4, 786–799 (2021).10.1038/s41928-021-00670-1 ↗
35. Cheng, Z. et al. How to report and benchmark emerging field-effect transistors. Nat. Electron. 5, 416–423 (2022).10.1038/s41928-022-00798-8 ↗
36. Li, K. S. et al. Negative-capacitance FinFET inverter, ring oscillator, SRAM cell, and Ft. In 2018 IEEE International Electron Devices Meeting (IEDM) 31.37.31–31.37.34 (IEEE, 2018).10.1109/IEDM.2018.8614521 ↗
37. Chang, S. W. et al. First demonstration of CMOS inverter and 6T-SRAM based on GAA CFETs structure for 3D-IC applications. In 2019 IEEE International Electron Devices Meeting (IEDM) 11.17.11–11.17.14 (IEEE, 2019).10.1109/IEDM19573.2019.8993525 ↗
38. Alam, M. H. et al. Lithium-ion electrolytic substrates for sub-1V high-performance transition metal dichalcogenide transistors and amplifiers. Nat. Commun. 11, 3203 (2020).
39. Conti, S. et al. Low-voltage 2D materials-based printed field-effect transistors for integrated digital and analog electronics on paper. Nat. Commun. 11, 3566 (2020).10.1038/s41467-020-17297-z ↗
40. Zhang, Q. et al. Simultaneous synthesis and integration of two-dimensional electronic components. Nat. Electron. 2, 164–170 (2019).10.1038/s41928-019-0233-2 ↗
41. Lin, Z. et al. Solution-processable 2D semiconductors for high-performance large-area electronics. Nature 562, 254–258 (2018).10.1038/s41586-018-0574-4 ↗
42. Li, N. et al. Large-scale flexible and transparent electronics based on monolayer molybdenum disulfide field-effect transistors. Nat. Electron. 3, 711–717 (2020).10.1038/s41928-020-00475-8 ↗
43. Zhang, X. et al. Molecule-upgraded van der Waals contacts for Schottky-barrier-free electronics. Adv. Mater. 33, 2104935 (2021).10.1002/adma.202104935 ↗
44. Pezeshki, A. et al. Static and dynamic performance of complementary inverters based on nanosheet α-MoTe2 p-channel and MoS2 n-channel transistors. ACS Nano 10, 1118–1125 (2016).10.1021/acsnano.5b06419 ↗
45. Lim, J. Y. et al. Homogeneous 2D MoTe2 p–n junctions and CMOS inverters formed by atomic-layer-deposition-induced doping. Adv. Mater. 29, 1701798 (2017).10.1002/adma.201701798 ↗
46. Li, W. et al. Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices. Nat. Electron. 2, 563–571 (2019).10.1038/s41928-019-0334-y ↗
47. Resta, G. V. et al. Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. In 2018 76th Device Research Conference (DRC) 1–2 (IEEE, 2018).10.1109/DRC.2018.8442152 ↗
48. Ngo, T. D. et al. Fermi-level pinning free high-performance 2D CMOS inverter fabricated with van der Waals bottom contacts. Adv. Electron. Mater. 7, 2001212 (2021).10.1002/aelm.202001212 ↗
49. Yang, X. et al. Highly reproducible van der Waals integration of two-dimensional electronics on the wafer scale. Nat. Nanotechnol. 18, 471–478 (2023).10.1038/s41565-023-01342-1 ↗
50. Tong, L. et al. Heterogeneous complementary field-effect transistors based on silicon and molybdenum disulfide. Nat. Electron. 6, 37–44 (2023).
51. Sachid, A. B. et al. Monolithic 3D CMOS using layered semiconductors. Adv. Mater. 28, 2547–2554 (2016).10.1002/adma.201505113 ↗
52. Tu, Y. & Tersoff, J. Structure and energetics of the Si–SiO2 interface. Phys. Rev. Lett. 84, 4393–4396 (2000).10.1103/PhysRevLett.84.4393 ↗
53. Peacock, P. W., Xiong, K., Tse, K. & Robertson, J. Bonding and interface states of Si:HfO2 and Si:ZrO2 interfaces. Phys. Rev. B 73, 075328 (2006).10.1103/PhysRevB.73.075328 ↗
54. Kc, S., Longo, R. C., Wallace, R. M. & Cho, K. Computational study of MoS2/HfO2 defective interfaces for nanometer-scale electronics. ACS Omega 2, 2827–2834 (2017).10.1021/acsomega.7b00636 ↗