Quantitative mechanism separation of single-event transients in nanosheet transistors via TCAD simulation

Abstract As process nodes scale to the nanosheet structure, the continuous reduction in device dimensions and the introduction of vertical stacking structures pose new challenges for single-event effect sensitivity. This work uses calibrated TCAD simulations to systematically investigate the effects of four key parameters—gate length, number of nanosheet stacks, sheet spacing, and drain voltage—on the single-event transient (SET) response of n-type nanosheet devices. By extracting the electron current integrals at the source and drain cross-sections, the relative contributions of the funneling effect and parasitic bipolar junction transistor (BJT) amplification mechanisms are quantitatively distinguished across different transient stages. The results reveal that the SET response exhibits a two-stage behavior: a prompt peak dominated by the funneling effect and modulated by gate length, drain voltage, and sensitive volume, and a delayed tail governed by the parasitic bipolar amplification, which depends on the intrinsic properties of the device structure. Reducing the gate length renders the parasitic BJT effect in the peak stage non-negligible. Increasing the number of stacks induces a nonlinear BJT amplification effect in the tail stage. The impact of sheet spacing on SET response is found to be minor. Drain voltage modulates only the peak stage without altering the tail attenuation characteristics. The two-stage mechanism elucidated in this work provides a physical foundation for radiation-hardened design in gate-all-around devices.