Logic and static memory functions of an inverter comprising a feedback field effect transistor

Abstract The von Neumann architecture used as the basic operating principle in computers has a bottleneck owing to the disparity between the central processing unit and memory access speeds, which leads to high power consumption and speed reduction, reducing the overall system performance. However, feedback field-effect transistors (FBFETs) have attracted significant attention owing to their potential to realize next-generation electronic devices based on their switching characteristics. Therefore, in this study, we configured the logic and static memory functions of an inverter comprising a pull-down resistor and an n-channel FBFET using a mixed-mode simulation. The FBFET has a p–n–p–n structure with a gated p-region on the silicon-on-insulator, where each channel length is 30 nm. These modes can have an on/off current ratio of ∼10¹¹ and a subthreshold swing of less than 5.4 mV dec⁻¹. The proposed device can perform logic operations and static memory functions, exhibiting excellent memory functions such as fast write, long hold, and non-destructive read operations. In addition, the inverter operation exhibits nanosecond-level speed and the ability to maintain non-destructive read functionality for over 100 s. The proposed n-FBFET-based inverter is expected to be a promising technology for future high-speed, low-power logic memory applications.