Hybrid-contact engineering for enhanced p-type performance in WSe₂ field-effect transistors

Abstract The development of high-performance p-type transition metal dichalcogenide field-effect transistors (FETs) is hindered by Fermi-level pinning (FLP) at metal-semiconductor interfaces, which creates large Schottky barriers and limits hole injection. This work introduces a hybrid-contact architecture, combining edge and top contacts, to mitigate FLP effects in WSe₂ FETs. By employing thermal scanning probe lithography and hard-mask etching, hybrid-contact devices were fabricated with minimal processing damage. Electrical characterization reveals that hybrid-contact configurations significantly enhance p-type conduction, achieving a 25-fold increase in hole current and reducing contact resistance to 3.96 kΩ μm⁻¹. Temperature-dependent measurements further confirm a low SBH of ∼34 meV for hole injection. The hybrid design demonstrates universal benefits for both p- and n-type operations but shows superior alignment with high-work-function metals (e.g., Pd, Au), enabling efficient hole transport. This approach provides a practical pathway for realizing complementary circuits and advancing post-silicon electronics.