Dislocation sink annihilating threading dislocations in strain-relaxed Si _{1− x} Ge _x layer

Abstract We proposed a dislocation sink technology for achieving Si _{1− x} Ge _x multi-bridge-channel field-effect-transistor beyond 5 nm transistor design-rule that essentially needs an almost crystalline-defect-free Si _{1− x} Ge _x channel. A generation of a dislocation sink via H ⁺ implantations in a strain-relaxed Si _0.7 Ge _0.3 layer grown on a Si substrate and a following annealing almost annihilate completely misfit and threading dislocations located near the interface between a relaxed Si _0.7 Ge _0.3 layer and a Si substrate. A real-time (continuous heating from room temperature to 600 °C) in situ high-resolution-transmission-electron-microscopy and inverse-fast-Fourier-transform image observation at 1.25 MV acceleration voltage obviously demonstrated the annihilation process between dislocation sinks and remaining misfit and threading dislocations during a thermal annealing, called the [Si _I or Ge _I + V _Si or V _Ge → Si _{1− x} Ge _x ] annihilation process, where Si _I , Ge _I , V _Si , and V _Ge are interstitial Si, interstitial Ge, Si vacancy, and Ge vacancy, respectively. In particular, the annihilation process efficiency greatly depended on the dose of H ⁺ implantation and annealing temperature; i.e. a maximum annihilation process efficiency achieved at 5 × 10 ¹⁵ atoms cm ⁻² and 800 °C.