Lab-based Nanoscale 3D X-Ray Microscopy for Failure Analysis on Advanced Semiconductors

3D X-Ray Microscopy (3D XRM) is a key method for analyzing modern semiconductor packages Due to its non-destructive nature, samples are investigated to find the root cause of dis-functions such as shorts, high resistive opens or electrical opens. Until recently, the main approach for lab-based X-Ray tomography measurements has been based on the principle of geometric magnification (so-called Micro-Computed Tomography or -CT) Here, the sample is placed between a broadband X-Ray source and detector and rotated around its axis while 2D X-Ray projections are acquired. The resulting resolution is then related to the sourcedetector distance and the spot size of the X-Ray source. 3D XRM extends this capability by using a photon-converting scintillator and optical objectives before the actual detector to achieve high resolution at larger sourcedetector distances. This procedure, known as resolution at a distance (RaaD [2]) enables the inspection of larger samples and a non-destructive semiconductor package workflow. Typically, the maximum resolution for this kind of method is in the order of 650 -700 nm with optimum conditions Continuous transistor node development, increased functionality density and 3D device build up in semiconductor products demands higher resolution X-Ray measurements Here, 3D XRM is regarded as promising and early publications have proven this to be feasible based on synchrotron results However, a lab-based method coupled to a repeatable and precise targeted sample preparation workflow is needed to meet the time-critical requirements of the semiconductor industry. A Fresnel Zone Plate (FZP) based solution using quasi-monochromatic X-rays from a laboratory source meets these needs. This XRM architecture allows a significant improvement in optical resolution down to 50 nm and less and opens application opportunities for imaging critical structures within the semiconductor build up, such as Back-end of Line (BEOL, the internal wiring of individual transistor, capacities, etc.) and Chip-Package-Interaction (CPI, the interconnect level between integrated circuit (IC) and substrate or different IC devices).